SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 36 -
- 36 -
https://www.acromag.com
100
62.5MHz
101
Undefined
N/A
110
External InB
CNTInB
111
External Clock Enable
(pin 49)
Up to 15MHz
14,13
Output and Interrupt Condition Select
00
No Output or Interrupt Selected
01
Output and Interrupt on counter equal Constant A
Register
10
Output and Interrupt on Index and reload on Index
11
Output and Interrupt on Index but do not reload
counter on Index.
15
Input Debounce Enable
0
Disabled (Default)
–
No Debounce Applied to any
Input.
1
Enabled
–
Reject A, B, or Index Pulses less than
or equal to 2.4
s.
An interrupt can be generated upon index reload, or when the counter value
equals the constant value stored in the Counter Constant A Register.
Interrupts must be enabled via the Enable/Disable Counter Interrupts
Register. The interrupt type must also be selected via bits 13 and 14 of the
Counter Control Register. The interrupt will remain pending until released
by setting the required bit of the Counter/Timer Interrupt Status/Clear
register. Note that interrupts in Quadrature Position Measurement are
generated whenever the interrupt conditions exist. If a pending interrupt is
cleared, but the interrupt conditions still exists, another interrupt will be
generated.
The Counter Control register bits 14 and 13 are used to control the
operation of the counter output signal. With bits 14 and 13
set to “01”, the
output signal will be driven active while the counter equals the counter
Constant A value. With bit 14
set to logic “1” the output signal will be driven
active while the index condition remains true.
Encoder output signals can be noisy. It is recommended that the InA, InB,
and InC input signals be debounced by setting bit-15 of the Counter Control
register to logic “1”.
Noise transitions less than 2.4
s will be removed with
debounce enabled.
