SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 23 -
http://www.acromag.com
- 23 -
https://www.acromag.com
Table 3.1 Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x7042 AP482
0x7043 AP483
0x7044 AP484
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space
(BAR0)
5:10
Not Used
11
Subsystem ID
0x7042 AP482
0x7043 AP483
0x7044 AP484
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
The memory space address map for the AP48X is shown in Table 3.2. Note
that the base address for the board (BAR0) in memory space must be added
to the addresses shown to properly access these AP48X registers. Register
accesses as 32, 16, and 8-bit data in memory space are permitted. All the
registers of the AP48X are accessed via data lines D0 to D31.
Table 3.2: AP482 Memory
Map
Notes:
1.
The AP will respond to
addresses that are
“Not Used”.
The board
will return “0” for all
address reads that are
not used or reserved.
BAR0 Base Address
Bit(s)
Description
0x0000 0000
7:0
Global Interrupt Enable and Pending
Status
0x0000 0004
15:0
Location in System Register
0x0000 0008
15:0
Counters Interrupt Status/Clear
Register
0x0000 000C
7:0
Counter Interrupt Enable/Disable
Register
