SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 20 -
- 20 -
https://www.acromag.com
Note 2:
APCe7020E-LF is an example
of a carrier that uses the Champ
connector see image of carrier.
Each 32-bit counter has three input and one output signal. For example
counter 1 has the input signals labeled IN1_A, IN1_B, IN1_C and the output
signal labeled OUT1.
2.5 Noise and Grounding Considerations
The board is non-isolated, since there is electrical continuity between the
logic and field I/O grounds. As such, the field I/O connections are not
isolated from the system. Care should be taken in designing installations
without isolation to avoid noise pickup and ground loops caused by multiple
ground connections.
2.6 Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2.2 and noted
below).
Threaded metric M2.5 screws and spacers are supplied with the AP module
to provide additional stability for harsh environments.
Power su5, +12, and -12 Volt have been assigned to pins that are
reserved in the mini-PCIe specification. The Present signal is grounded on
the AP module. In addition, COEX1, COEX2
–
wireless transmitter control
are reassigned to JTAG signals TMS and TCK. Lastly, UIM_C4, UIM_C8
–
reserved User Identity Module signals are reassigned to JTAG signals TDI and
TDO.
Table 2.4: Logic Interface
Connections
