SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 42 -
- 42 -
https://www.acromag.com
starts counting from 0 and since the counter would match the count-to value
the counter resets and starts counting from zero again.
If interrupts are enabled via the Enable/Disable Interrupts Register, an
interrupt is generated when the number of input pulse events is equal to the
Counter Constant A register value. The internal counter is then cleared and
will continue counting events until the counter constant A value is again
reached and a new interrupt generated. An interrupt will remain pending until
released by setting the required bit of the Counters Interrupt Status/Clear
register.
Table 3.14 Counter Control
Register (Event Counting)
1. The default state of the
output pin is high (output has
pullup resistor installed). Bit
3 specifies the active output
polarity when the output is
driven.
Bit(s)
FUNCTION
2,1,0
Specifies the Counter Mode:
100
Event Counting
3
Output Polarity (Output Pin ACTIVE Level):
0
Active LOW (Default)
1
1
Active HIGH
5, 4
InA Polarity / Gate-Off
00
Disabled (Default)
01
Active LOW
In A=0: Continue Counting
In A=1: Stop Counting
10
Active HIGH
In A=0: Stop Counting
In A=1: Continue Counting
InA Hardware Capture Count Mode
11
InA = logic high pulse: Causes load of the Read Back
register
InA = 1: Load Read Back Register with Current Count
7, 6
InB Polarity / Event Input
00
Disabled (Default)
01
Active LOW Events
10
Active HIGH Events
11
Disabled
9,8
InC Polarity / External Trigger
00
Disabled (Default)
01
Active LOW Trigger
10
Active HIGH Trigger
11
Count Up when logic low /Down when logic high
Count Control
12,11,10 Specifies the Counter Mode:
000
Event Counting
14 ,13
Not Used (bits read back as 0)
15
Input Debounce Enable
0
Disabled (Default)
–
No Debounce Applied to any
Input.
