SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 40 -
- 40 -
https://www.acromag.com
pending until the watchdog timer is reinitialized and the interrupt is
released by setting the required bit of the Counter/Timer Interrupt
Status/Clear
register.
Table 3.13 Counter Control
Register (Watchdog Timer)
1. The default state of the
output pin is high (output has
pullup resistor installed). Bit 3
specifies the active output
polarity when the output is
driven.
Bit(s)
FUNCTION
2,1,0
Specifies the Counter Mode:
011
Watchdog Function
3
Output Polarity (Output Pin ACTIVE Level):
0
Active LOW (Default)
1
1
Active HIGH
5, 4
InA Polarity / Counter Reload
00
Disabled (Default)
01
Active LOW
In A=0 Counter Reinitialized
In A=1 Inactive State
10
Active HIGH
In A=0 Inactive State
In A=1 Counter Reinitialized
11
Disabled
7, 6
InB Polarity / External Clock Input
00
Disabled (Default)
01
External Clock Enabled
10
External Clock Enabled
11
Disabled
9,8
InC Polarity / External Trigger
00
Disabled (Default)
01
Active LOW Trigger
10
Active HIGH Trigger
11
Gate-Off (Continue when high/Stop when low)
12,11,10
Clock Enable Frequency
000
Internal (Default)
1.953125MHz
001
Internal
3.90625MHz
010
Internal
7.8125MHz
011
Internal
15.625MHz
100
Internal
62.5MHz
101
Undefined
N/A
110
External InB
CNTInB
111
External Clock (pin
49)
Up to 15MHz
14 ,13
Not Used (bits read back as 0)
15
Input Debounce Enable
0
Disabled (Default)
–
No Debounce Applied to any
Input.
