4. FDC Description (82078)
27
Configuration Control Register (CCR)
3F7h Default
This register sets the data rate and is write only. In the PC/AT it is named the DSR.
7
6
5
4
3
2
1
0
DRATE
SEL1
IDLE-
DRATE
SEL0
MASK
Configuration Control Register
Refer to the "
Data Rates
" table in the "Datarate Select Register" section of this chapter
for values.
Bit 4, IDLEMASK, is used to mask the IDLE pin on the 82078, which is not used on the
ZT 8954. Its use can be ignored and should be left enabled (logic 0).
Unused bits should be set to 0.
RESET
As discussed in the following topics, the 82078 has three sources of reset: the RESET
pin; a reset generated via a bit in the DOR; and a reset generated via a bit in the DSR.
All resets take the 82078 out of the power down state.
On entering the reset state, all operations are terminated and the 82078 enters an idle
state. Activating reset while a disk write activity is in progress will corrupt the data and
CRC.
On exiting the reset state, various internal registers are cleared, including the
CONFIGURE command information, and the 82078 waits for a new command. Drive
polling will start unless disabled by a new CONFIGURE command.
RESET Pin
The RESET pin is a global reset and clears all registers except those programmed by
the SPECIFY command. The DOR Reset bit is enabled and must be cleared by the host
to exit the reset state.
DOR Reset vs. DSR Reset
These two resets are functionally the same. The DSR Reset is included to maintain
82072 compatibility. Both reset the 82078 core, which affects drive status information
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