4. FDC Description (82078)
20
Digital Output Register (DOR)
3F2h Default
The Digital Output Register contains the drive select and motor enable bits, a reset bit,
and a DMAGATE* bit. This register is used in both PC/AT and PS/2 designs. The 8954
is shipped with the IDENT pin in PS/2 configuration.
7
6
5
4
3
2
1
0
DRIVE
SEL1
MOT
RESET
EN3
MOT
EN0
MOT
EN2
MOT
EN1
DRIVE
SEL0
DMA
GATE*
Digital Output Register
Bits 4-7, the MOT ENx bits, directly control their respective motor enable pins (ME0-3).
A 1 means the pin is active. Bits 0 and 1, the DRIVE SELx bits, are decoded to provide
four drive select lines; only one may be active at a time. Since the ZT 8954 ties INVERT
low, these signals are active low on the interface. Standard programming practice is to
set both MOT ENx and DRIVE SELx bits at the same time. The "
Drive Activation
Values
" table lists a set of DOR values to activate the drive select and motor enable for
each drive.
Bit 3, the DMAGATE* bit, is not enabled on the ZT 8954. DMAGATE* has no effect
upon the INT and DRQ pins, and they are always active.
Bit 2, the RESET* bit, clears the basic core of the 82078 and the FIFO circuits. Once
set, it remains set until you clear it. This bit is set by a chip reset and the 82078 is held
in a reset state until you clear this bit. The RESET* bit has no effect upon this register.
The RESET* pin clears this register.
Drive Activation Values
Drive
DOR Value
0
1Ch
1
2Dh
2
4Eh
3
8Fh
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