B. Specifications
35
STD 32 Bus Loading, P Connector
Notes to the STD Bus Loading Diagram
[A] is the logic supply drain = 2.0 Amps max.
[B] PCI and PCO are shorted together.
[C] High order address bits multiplexed over data bus D0-D7.
[NC] No Connection.
+5 VOLTS [A]
GROUND
DCPDN* [NC]
D7 (A23)
D6 (A22)
D5 (A21)
D4 (A20)
A15
A14
A13
A12
A11
A10
A9
A8
RD*
MEMRQ*
BHE
ALE*
STATUS 0*
BUSRQ*
INTRQ*
NMIRQ*
PBRESET* [NC]
INTRQ2* (CNTRL*)
PCI [B]
AUX GND
AUX-V
+5 VOLTS [A]
GROUND
VBATT [NC]
D3 (A19)
D2 (A18)
D1 (A17)
D0 (A16)
A7
A6
A5
A4
A3
A2
A1
A0
WR*
IORQ*
IOEXP
INTRQ1*
STATUS 1*
BUSAK*
INTAK* [NC]
WAITRQ*
SYSRESET*
CLOCK*
PCO [B]
AUX GND
AUX+V
2
4
6
1
3
5
1
1
1
1
59
59
59
59
8
10
12
14
7
9
11
13
59
59
59
59
1
1
1
1
1
1
1
1
16
18
20
22
15
17
19
21
1
1
1
1
1
2
2
2
1
1
1
24
26
28
30
23
25
27
29
32
34
36
38
31
33
35
37
60
60
60
40
42
44
46
39
41
43
45
1
48
50
52
47
49
51
1
1
60
1
54
56
53
55
PIN (CIRCUIT SIDE)
OUTPUT DRIVE
INPUT LOAD
MNEMONIC
PIN (COMPONENT SIDE)
OUTPUT DRIVE
INPUT LOAD
MNEMONIC
[C]
[C]
[C]
[C]
[C]
[C]
[C]
[C]
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