4. FDC Description (82078)
23
down mode and power-down via the POWER DOWN bit have no effect over the power
state of the oscillator.
In the default state the PDOSC bit is low and the oscillator is powered up. When this bit
is programmed to a 1, the oscillator is shut off. Hardware reset clears this bit to 0.
Neither of the software resets has any effect on this bit. Note that PDOSC should be set
high only when the part is in the power-down state; otherwise, the part will not function
correctly and must be hardware reset once the oscillator has turned back on and
stabilized.
Bits 2-4, PRECOMP 0-2, adjust the WRDATA output to the disk to compensate for
magnetic media phenomena known as "bit shifting." The data patterns that are
susceptible to bit shifting are well understood and the 82078 compensates the data
pattern as it is written to the disk. The amount of precompensation is dependent upon
the drive and media, but in most cases the default value is acceptable.
The 82078 starts precompensating the data pattern on Track 0. The CONFIGURE
command can change the track on which precompensating starts. The following
"Precompensation Delays" table lists the precompensation values that can be selected,
and the "Default Precompensation Delays" table lists the default precompensation
values. The default value is selected if the three bits are zeros.
Bits 0 and 1, DRATESEL 0-1, select one of the four data rates as listed in the "Data
Rates" table below. The default value is 250 Kbps upon a chip reset. Other resets do
not affect the DRATE or PRECOMP bits.
Data Rates
DRATESEL1
DRATESEL0
DATARATE
1
1
1 Mbps
0
0
500 Kbps
0
1
300 Kbps
1
0
250 Kbps
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
