4. FDC Description (82078)
26
FIFO Service Delay
1 Mbps Data Rate
FIFO Threshold
Examples
Maximum Delay to Servicing at
1 Mbps Data Rate
1 byte
1 x 8 µs - 1.5 µs = 6.5 µs
2 bytes
2 x 8 µs - 1.5 µs = 14.5 µs
8 bytes
8 x 8 µs - 1.5 µs = 62.5 µs
15 bytes
15 x 8 µs - 1.5 µs = 118.5 µs
500 Kbps Data Rate
FIFO Threshold
Examples
Maximum Delay to Servicing at
500 Kbps Data Rate
1 byte
1 x 16 µs - 1.5 µs = 14.5 µs
2 bytes
2 x 16 µs - 1.5 µs = 30.5 µs
8 bytes
8 x 16 µs - 1.5 µs = 126.5 µs
15 bytes
15 x 16 µs - 1.5 µs = 238.5 µs
Digital Input Register (DIR)
3F7h Default
This register senses the state of the DSKCHG input and is read-only.
7
6
5
4
3
2
1
0
ND
DSK
CHG
ND
ND
ND
ND
ND
ND
ND: Not driven by ZT 8954
Digital Input Register
Bit 7 , DSKCHG, monitors the pin of the same name and reflects the opposite value
seen on the disk cable. Bits 0-6 are not driven by the ZT 8954.
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