Xycom XVME-240, Руководство пользователя

Страница: 58 / 73

XVME-240 Manual
October, 1984
Signal
Mnemonic
DTACK*
D00-D15
G N D
IACK* 1A:
20
IRQl*-
IRQ7*
LWORD* lC: 13
(RESERVED)
2B: 3
SERCLK
1B: 21
SERDAT
1B: 22
Table
B-l. VMEbus Signal Identification (cont’d)
Connector
and
Pin Number
1A:16
IA: l-8
lC: l-8
IA: 9,ll,
15,17,19
1B: 20,23
lC: 9
2B: 2,12
22,31
IB:
24-30
Signal Name and Description
DATA TRANSFER ACKNOWLEDGE - Open-
collector driven signal generated by a DTB slave.
The failing edge of this signal indicates that valid
data is available on the data bus during a read
cycle, or that data has been accepted from the
data bus during a write cycle.
DATA BUS (bits 0- 15) - Three-state driven bi-
directional data lines that provide a data path
between the DTB master and slave.
GROUND
INTERRUPT ACKNOWLEDGE - Open-collector or
three-state driven signal from any Master proces-
sing an interrupt request. Routed via the back-
plane to Slot 1, where it is looped back to become
Slot 1 IACKIN* to start the interrupt acknowledge
daisy-chain.
INTERRUPT REQUEST (l-7) - Open-collector dri-
ven signals, generated by an interrupter, which
carry prioritized interrupt requests. Level seven is
the highest priority.
LONGWORD - Three-state driven signal to indi-
cate that the current transfer is a 32-bit transfer.
RESERVED - Signal line reserved for future
VMEbus enhancements. This line must not be used.
A reserved signal which will be used as the clock
for a serial communication bus protocol which is
still being finalized.
A reserved signal which will be used as the
transmission line for serial communication bus
messages.
B-3