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XVME-560 Manual

September, 1984

base addresses in 1K (400H) increments. On an intelligent XVME module, address

signals Al0-A13 are decoded, while Al4 and Al5 must be zero. (This implies that only

the lowest 16 of the possible 64 1K segments are used for intelligent modules.) On

non-intelligent

XVME

modules, the six highest order short I/O address bits are

decoded, while the remaining lower order bits are ignored. This arrangement provides

the correct address configuration to allow each module address to begin on a 1K

boundary. Non-intelligent XVME modules allow the use of six base address jumpers

(representing bits Al0-A15), and thus, they are able to reside on any of the 64

boundaries available in the short I/O address space. Intelligent XVME modules will

only allow the use of four base address jumpers (representing bits AI0-A13) which

limits their selection of 1K boundaries to one of 16 possible choices.

Figure A-l shows an abbreviated view of the short I/O memory.

BASE

08OOH

Short I/O

Address Space

Figure A-1. 64K Short I/O Address Space

A-2

Содержание XVME-240

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Страница 6: ...s and functional capabilities of the DIO module Successive chapters will develop the various aspects of module installation and operation in the following progression Chapter One A general description...

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Страница 8: ...ort I O Address space I O Interface Block The DIO occupies a IK block of the Short I O Address space called the module I O Interface Block Within this block in standard locations are found the I O reg...

Страница 9: ...el output voltage Io1 48mA Io1 16 mA Iol Low level output current Voh High level output voltage Ioh High level output current Voh 2 4V Ioh 2 OV Slave Data Transfer Options A16 D16 STAT A24 D16 STAT In...

Страница 10: ...l to 50 000 ft 15240m Vibration Operating 5 to 2000 Hz 0 015 inches peak to peak displacement 2 5 g peak max acceleration Non Operating I 5 to 2000 Hz 030 inches peak to peak displacement 5 0 g peak m...

Страница 11: ...employs a Data Transfer Bus Arbiter a Subsystem Clock driver a System Reset driver and a Bus time out module The XYCOM XVME 010 System Resource Module provides a controller subsystem with the compone...

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Страница 13: ...rs for Short I O Address Space or those for Standard Memory space 2 4 l Base Address Switches The DIO module is designed to be addressed within either the VMEbus Short I O or Standard Memory Space Sin...

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Страница 16: ...itch 8 must be set to open If jumper J2B is installed Switch 8 must be set to closed The Standard I O Architecture recommends that the DIO operate within the Short I O Address Space in order to take a...

Страница 17: ...ed Open Privilege Mode Selected Supervisory or Non Privileged Supervisory Only 2 4 4 Address Modifier Reference The following table Table 2 5 indicates the actual VMEbus Address Modifier code that the...

Страница 18: ...nable the IACKIN IACKOUT daisy chain CAUTION The jumper shorting IACKIN to IACKOUT for the DIO s slot in the backplane must be removed or the DIO may be damaged 2 4 6 Interrupt Level Switches Figure 2...

Страница 19: ...BGxOUT x 0 thru 3 Since these signals are already hardwired on the DIO it is not necessary to insert these VMEbus jumpers on the slot occupied by the DIO 2 4 8 Interrupt Input Edge Detection Option Th...

Страница 20: ...Jl0 If a jumper is set in position A then that interrupt input line will latch the interrupt input on the low to high transition of the signal Likewise if a jumper is set to posi tion B then that int...

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Страница 22: ...3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 12 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 1 21 1 22 l 23 24 2 5 2 2 6 2 2 7 2 2 8 2 2 9 2 3 0 2 31 2 3 2 2 3 3 2 Definition CONNECTOR JK 1 Data Bit 0 Data Bit 1 Dat...

Страница 23: ...rrupt Input Register 4 6 3 Flag Output Line Bit 3 of Flag Output Register 4 7 GND 4 8 GND 4 9 GND 50 GND CONNECTOR JK 2 1 4 Data Bit 0 2 4 Data Bit 1 3 4 Data Bit 2 4 4 Data Bit 3 5 4 Data Bit 4 6 4 D...

Страница 24: ...a Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Interrupt Input Line Bit 6 of Interrupt Input Register Flag Output Line Bit 6 of Flag Output Register GND GND Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data...

Страница 25: ...y for the operation of VMEbus defined NEXP modules The Pl connector is designed to mechanically interface with a VMEbus defined Pl backplane The P2 connector is a standard VMEbus P2 backplane connecto...

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Страница 27: ...of the chassis opening Center the board on the plastic guides so that the solder side is facing to the left and the component side is facing to the right refer to Figure 2 7 Push the card slowly towa...

Страница 28: ...DIO module is installed it will occupy a 1K byte block of the Short I O Address space referred to as the module I O Interface Block The starting address for each I O Interface Block must reside on a...

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Страница 30: ...arts at F9OOOOH and if the base address of the DIO is jumpered to 1000H the actual module base address would be F9l000H 3 3 THE DIO I O INTERFACE BLOCK The 1K block of Short I O Address space allotted...

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Страница 32: ...finitions for the DIO Status Control byte STATUS CONTROL REGISTER Base Address 081H Red LED SYSFAIL InterruptPending Interrupt Enable Software Reset User Available Flag Bits Figure 3 2 Status Control...

Страница 33: ...Status Module failed or not yet tested Inactive module Module undergoing test Module passed test NOTE The DIO is a non intelligent module so all diagnos tics and configuration checking must be perfor...

Страница 34: ...the same time The direction of each port is determined by the contents of the read write Port Direction Register Base address 87H Each bit in the Port Direction register corresponds to one of the I O...

Страница 35: ...low user software firmware to determine which externally connected device is sending an interrupt Each interrupt input has its own Interrupt Edge Detection circuitry and interrupt latch refer to Secti...

Страница 36: ...be a logic 0 3 3 5 Interrupt Clear Register Base Address 84H The Interrupt Clear Register provides the user with the means to clear interrupt input latches and registers These latches and registers w...

Страница 37: ...ear Register should be used after power up or reset to clear all interrupt input latches and registers prior to enabling interrupts SYSRESET and Soft Reset do not clear interrupt input latches 3 3 6 I...

Страница 38: ...change the mask is to write a new value to the module base address 83H Writing FFH to the Interrupt Mask Register would pass all latched interrupts and writing 00H to the register would mask out all l...

Страница 39: ...rrupt Logic 0 No Pending Interrupt Figure 3 7 Interrupts Pending Register When reading the Interrupts Pending Register Base address 82H a bit containing a 1 means that the corresponding interrupt inpu...

Страница 40: ...sed is dependent upon the system processor Please refer to your system processor operating manual for information on interrupt vectors 3 3 9 Flag Outputs Register Base Address 86H The DIO provides 8 F...

Страница 41: ...S SUMMARY The DIO module has been designed to receive interrupt input signals from externally connected devices in order to generate a VMEbus Interrupt Request to a system processor There are 8 Interr...

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Страница 43: ...ile the corresponding mask bit is set to 0 it will be prevented from passing through the mask but if the same mask bit is written a 1 before the latch is cleared the interrupt signal will pass through...

Страница 44: ...r up or reset 3 Clear Interrupt Input latches and registers by writing to the Interrupt Clears register 4 Write the Vector address which is to be employed by interrupt handling software in the Interru...

Страница 45: ...upts The pending interrupts can now be serviced by the handler routine in the same fashion as shown above Interrupts can be disabled in one of three ways 1 By resetting the system i e the Mask Registe...

Страница 46: ...of the module to interrupt the system Communication between Modules How master host processors and intelligent I O modules communicate through shared global memory or the dual access RAM on the I O mo...

Страница 47: ...ovides the correct address configuration to allow each module address to begin on a 1K boundary Non intelligent XVME modules allow the use of six base address jumpers representing bits Al0 A15 and thu...

Страница 48: ...rea of the module I O Interface Block base address 82H roughly l2OF is module specific and it varies in size from one module to the next It is in this area that the module holds specific I O status da...

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Страница 52: ...if the board is operating properly On non intelligent XVME I O modules the status control register is used to indicate the state of the front panel LEDs and to set and verify module generated interru...

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Страница 54: ...rnels common from module to module Each different module type consists of a standard kernel combined with module dependent application circuitry Module standardiza tion results in more efficient modul...

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Страница 56: ...l9 C 14 A 18 1A 24 30 ADDRESS bus bits l 23 Three state driven l C 15 30 address lines that specify a memory address Signal Name and Description AC FAILURE open collector driven signal which indicates...

Страница 57: ...pole driven signals generated by the Arbiter or Requesters Bus Grant In and Out signals from a daisy chained bus grant The Bus Grant In signal indicates to this board that it may become the next bus m...

Страница 58: ...between the DTB master and slave GROUND INTERRUPT ACKNOWLEDGE Open collector or three state driven signal from any Master proces sing an interrupt request Routed via the back plane to Slot 1 where it...

Страница 59: ...al may be generated by any module on the VMEbus SYSRESET 1C 12 SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE 1A 14 WRITE Three state driven signal th...

Страница 60: ...Row B Row C Signal Signal Signal Mnemonic Mnemonic Mnemonic D00 BBSY DO8 DO1 BCLR DO9 DO2 ACFAIL DlO DO3 BGOIN Dll DO4 I BG0OUT D12 DO5 BGlIN D13 DO6 BGlOUT D14 DO7 BG2IN D15 GND BG20UT GDN SYSCLK BG...

Страница 61: ...Number Signal Name and Description 5 Vdc Power Used by system logic circuits 2G 2 12 22 31 Ground ALL OTHER PINS NOT USED BACKPLANE CONNECTOR P2 The following table lists the P2 pin assignments by pi...

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Страница 71: ...ned Module Identification Undefined I Interrupt inputs Status Control Interrupts Pend Interrupt Mask Interrupt Clear Interrupt Vector Flag Outputs Port Direction I O Port 0 I O Port I I O Port 2 I O P...

Страница 72: ...Block Sl Function Selects VMEbus Interrupt Request Level for module I1 17 S2 switches l 6 S2 switch 7 S2 switch 8 Selects Module Base Address This switch works in conjunction with jumper J2 to determi...

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