XVME-240 Manual
October, 1984
Appendix A
XYCOM STANDARD I/O ARCHITECTURE
INTRODUCTION
The purpose of this Appendix is to define XYCOM's Standard I/O Architecture for
XVME I/O modules.
This Standard I/O Architecture has been incorporated on all
XVME I/O modules in order to provide a simpler and more consistent method of
programming for the entire module line.
The I/O Architecture specifies the logical
aspects of bus interfaces, as opposed to the “physical” or electrical aspects as defined
in the VMEbus specifications. The module elements which are standardized by the
XYCOM I/O Architecture are the following:
Module Addressing - - Where a module is positioned in the I/O address
space and how software can read from it or write to it.
Module Identification -- How software can identify which modules are
installed in a system.
Module Operational Status -- How the operator can (through software)
determine the operational condition of specific modules within the system.
Interrupt Control -- How software is able to control and monitor the
capability of the module to interrupt the system
Communication between Modules -- How master (host) processors and
intelligent I/O modules communicate through shared global memory
or
the
dual-access RAM on the I/O modules.
The I/O Kernel -- How intelligent and non-intelligent "kernels" facilitate
the operation of all XYCOM I/O modules.
MODULE ADDRESSING
All XYCOM I/O modules are designed to be addressed within the VMEbus-defined 64K
short I/O address space. The restriction of I/O modules to the short I/O address space
provides separation of program/data address space and the I/O address space. This
convention simplifies software design and minimizes hardware and module cost, while
at the same time, providing 64K of address space for I/O modules.
Base Addressing
Since each I/O module connected to the bus must have its own unique base address, the
base addressing scheme for XYCOM VME I/O modules has been designed to be jumper-
selectable. Each XVME I/O module installed in the system requires at least a 1K byte
block of the short I/O memory.
This divides the 64K short I/O address space into 64
1K segments.
Thus, each I/O module has a base address which starts on a 1K
boundary. As a result, the XYCOM I/O modules have all been implemented to decode
A-l
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