Xycom XVME-240, Руководство пользователя

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XVME-240 Manual
October, 1984
INTERRUPT MASK REGISTER Base A 83H)
Bit Bit
Bit Bit Bit
Bit
Bit Bit
7 6 5 4 3 2 1 0
Interrupt Input Latch 0
Interrupt Input Latch 1
Interrupt Input Latch 2
Interrupt Input Latch 3
Interrupt Input Latch 4
Interrupt Input Latch 5
Interrupt Input Latch 6
Interrupt Input Latch 7
Writing a "1" will "pass" an interrupt.
Writing a
" 0 "
will mask out an interrupt.
Figure 3-6. Interrupt Mask Register
For example, in order to mask out all latched interrupts except those latched on
Interrupt Input 3, a value of 04H must be written to the module base a 83H.
This will put a "1" in the fourth bit (interrupt input 3) and "0"s in all other bits. As
long as this "mask" is in the register the only latched interrupts that will be “passed
through” are those occurring on interrupt input 3. The only way to change the mask is
to write a new value to the module base a 83H.
Writing FFH to the Interrupt Mask Register would pass all latched
interrupts and
writing 00H to the register would mask out all latched interrupts.
NOTE
The Interrupt Mask Register is set to all " 0 " s (all
interrupts
masked out) immediately following
SYSRESET or Soft Reset. In order to properly
enable interrupts, the user software/firmware will
have to write the correct masks to the Mask Reg-
ister
l
3.3.7 Interrupts Pending Register (Base A 82H)
The contents of this “read only" register can be studied by user-provided software/
firmware to determine if there are latched interrupts which have passed through the
interrupt mask (if any) and are waiting to be serviced. This register directly relates to
Bit 2 of the Status/Control register (refer to Section 3.3.2). If any bit in this register
is set,
Bit
2 of the Status/Control Register will also be set. Thus, Bit 2 of the
Status/Control Register shows if there are any pending interrupts at all, and the
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