Xycom XVME-240, Руководство пользователя

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XVME-240 Manual
October, 1984
Enable bit, the interrupt capability of the DIO module is disabled.
Any interrupt
signals which are latched in and passed through the
Interrupt Mask while
interrupts are
disabled will remain pending until the interrupts are enabled, cleared, or masked out.
Once a backplane interrupt signal (Il-I7 as determined by the
setting
of switch Sl) is
generated, it will remain active until the system software clears the Interrupt Input
latch by writing to the Interrupt Clear Register. The backplane interrupt signal is not
cleared by the Interrupt Acknowledge cycle.
NOTE
The Interrupt Vector Register and the Interrupt
Input latches will contain undeterminate data on
power-up and reset.
Thus, before interrupts are
enabled, the interrupt latches must be cleared and
the Interrupt Vector address must be programmed.
3.4.1
Interrupt Sequence
The following section covers the interrupt initialization sequence and a typical
interrupt execution sequence.
With
1)
2)
the power off:
Determine and set the correct positions for the Interrupt Edge Detector jumpers.
Select the desired Interrupt Request level for the DIO module using Switch Sl.
After system power-up (or reset):
3)
Clear Interrupt Input latches and registers by writing to the Interrupt Clears
register.
4)
Write the Vector address (which is to be employed by interrupt handling
software) in the Interrupt Vector register.
5)
Write an appropriate mask to the Interrupt Mask register to enable the interrupt
inputs for the desired input lines.
6)
Enable the DIO module interrupt capability by writing to Bit 3 of the
Status/Control register.
At this point the module is ready to receive interrupt input signals from externally
connected devices. Typically, user software/firmware would be set up to monitor Bit
2 of the Status/Control register (Interrupt Pending Flag). When a pending interrupt is
detected, the Interrupt Pending register could be read to determine which device(s) is
(are) sending the interrupt(s). If more than one interrupt is pending concurrently, it is
the responsibility of user service routines to prioritize the interrupts.
As each
interrupt is handled, the Flag Output lines can be used to notify the interrupting
devices that servicing is complete. When an interrupt is serviced and the interrupting
device is notified, the corresponding Interrupt Input latch should be cleared by writing
to the Interrupt Clear Register.
If there are still interrupts pending, the procedure
can be repeated for each one. Once all pending interrupts -have been serviced, the
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