Xycom XVME-240, Руководство пользователя

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XVME-240 Manual
October, 1984
in the I/O Interface Block, and if the base address of the module is set at l000H, then
I/O Port 3 can be accessed at 108BH.
(Module Base
Address)
l000H +
(I/O Interface
(I/O
Block Offset)
Port 3)
8BH
=
108BH
The I/O ports are all read/write registers and they can be read from or written to at
any time. The data read will always reflect the state of the actual port lines. The
data latch for each port is cleared to OOH during any VME SYSRESET or software
reset.
3.3.3.1 Port Direction Register (Base A 87H)
As mentioned in the previous section, the 8 I/O ports are bidirectional. This means
that each port can operate as an output port or as an input port (not both at the same
time). The direction of each port is determined by the contents of the (read/write)
Port Direction Register (Base a 87H). Each bit in the Port Direction register
corresponds to one of the I/O ports. Bit 0 corresponds to Port
0,
bit 1 corresponds to
Port 1, and so on. When a logic "0" is written to a specific bit in the Port Direction
register, the port corresponding to that bit will be configured as an input port. When a
logic "1" is written to a specific bit in the register, the corresponding port will be
configured as an output port. Figure 3-3 is a bit map of the Port Direction register.
PORT DIRECTION REGISTER (module Base + 87H)
t
Bit Bit
l
Bit
Bit Bit Bit Bit Bit
7 6 5 4
3 2
1 0
I
I .
Port 0
I
I/O Port 3
I/O Port 4
I/O Port 5
I
A logic " 1 " configures a Port for output.
A logic "0" configures a Port for input.
I/O Port 6
I/O Port 7
Figure 3-3. Port Direction Register Bit Map
3-7