Xycom XVME-240, Руководство пользователя

Страница: 37 / 73

XVME-240 Manual
October, 1984
Each bit of the Interrupt Clear Register is connected to a specific interrupt input
latch. By writing a "1" to a particular bit position in the Clear Register, you will clear
the corresponding interrupt input latch and register. For example, if a module base
address is set to lOOOH
(in Short I/O Address Space) and it is necessary to clear
interrupt input latches for input 0 and input 2, then you would write 05H to address
1084H. This will put a logic "1" in bit positions 0 and 2 in the Interrupt Clear
Register,
and thus clear the interrupt input latches for inputs 0 and 2.
The Interrupt Clear Register resets itself after it has been written to and therefore
needs no additional attention from user programs. Attempting to read from the
register will not affect the interrupt input latches or registers, but it will return
indeterminate data.
The Interrupt Clear Register should be used after power-up or reset to clear all
interrupt input latches and registers prior to enabling interrupts. SYSRESET and Soft
Reset do not clear interrupt input latches.
3.3.6 Interrupt Mask Register (Base A 83H)
This "read/write" register can be employed by user software/firmware to "mask" out
certain Interrupt Inputs and thus prevent some devices from generating interrupts
temporarily. Typically, a "mask" might be employed to keep a group of devices from
generating interrupts while the interrupt from another device is being serviced.
The Interrupt Mask Register is positioned immediately
following
the interrupt
input
latch.
Each
bit of the Interrupt Mask Register corresponds to a specific interrupt
input latch output. When a logic "1" is written to a specific bit in the register, the
corresponding interrupt input line will be able to "pass" a latched interrupt through the
mask. When a logic "0" is written to a specific bit in the
register, the correspodng
latched
interrupt input will be blocked.
Figure 3-6 is a bit map of the Interrupt Mask Register.
3-10