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XAUI v12.3 Product Guide
24
PG053 April 6, 2016
Chapter 2:
Product Specification
gt2_rxrate_in[2:0]
in
Reserved
This port dynamically controls the setting for the RX
serial clock divider.
GT2 Loopback
gt2_loopback_in[2:0]
in
Async
Determines the loopback mode.
GT2 Polarity
gt2_rxpolarity_in
in
clk156_out The rxpolarity port can invert the polarity of incoming
data.
gt2_txpolarity_in
in
clk156_out The txpolarity port can invert the polarity of outgoing
data.
GT2 RX Decision Feedback Equalizer (DFE)
gt2_rxlpmen_in
in
Async
(GTXE2 and GTHE2) RX datapath.
0: DFE.
1: LPM.
gt2_rxdfelpmreset_in
in
Async
(GTXE2 and GTHE2) Reset for LPM and DFE datapath.
gt2_rxmonitorsel_in[1:0]
in
Reserved
(GTXE2 and GTHE2) Select signal for
gt2_rxmonitorout_out
.
gt2_rxmonitorout_out[6:0]
out
Async
(GTXE2 and GTHE2) Monitor output.
gt2_rxlpmreset_in
in
clk156_out (GTPE2) This port is driven High and then deasserted to
start the LPM reset process.
gt2_rxlpmhfhold_in
in
Async
(GTPE2) Determines whether the value of the
high-frequency boost is either held or adapted.
gt2_rxlpmhfovrden_in
in
Async
(GTPE2) Determines whether the high-frequency boost
is controlled by an attribute or a signal.
gt2_rxlpmlfhold_in
in
Async
(GTPE2) Determines whether the value of the
low-frequency boost is either held or adapted.
gt2_rxlpmlfovrden_in
in
Async
(GTPE2) Determines whether the low-frequency boost
is controlled by an attribute or a signal.
GT2 TX Driver
gt2_txpostcursor_in[4:0]
in
Async
Transmitter post-cursor TX post-emphasis control.
gt2_txprecursor_in[4:0]
in
Async
Transmitter post-cursor TX pre-emphasis control.
gt2_txdiffctrl_in[3:0]
in
Async
Driver Swing Control.
gt2_txinhibit_in
in
clk156_out When High, this signal blocks the transmission of data.
GT2 PRBS
gt2_rxprbscntreset_in
in
clk156_out Resets the PRBS error counter.
gt2_rxprbserr_out
out
clk156_out This non-sticky status output indicates that PRBS
errors have occurred.
gt2_rxprbssel_in[2:0]
in
clk156_out Receiver PRBS checker test pattern control.
Table 2
‐
8:
Transceiver Control and Status Ports —7 Series FPGAs
(Cont’d)
Signal Name
Direction
Clock
Domain
Description