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KCU1250 User Guide

www.xilinx.com

UG1057 (v1.0) December 19, 2014

Appendix D:

System Controller

This option returns to the menu level above.

PMBus Menu

The PMBus bus commands are used to read the voltage settings of the KCU1250 board

power rails controlled by the Maxim power system. Through the PMBus menu these power

rails can be read once or scanned continuously until stopped by a key press.

Table D-1

lists

the voltage rails accessible through the system controller's interface to the Maxim PMBus.

Table D-1:

Voltage Rails Accessible Through System Controller’s Interface to PMBus

Maxim Power Supply Rail

I2C Address

Nominal Voltage

VCCINT

0x0A

0.95V

VCCAUX

0x0B

1.80V

VCCBRAM

0x0F

0.95V

VCCO_HP

0x13

1.80V

VCCO_HR

0x11

1.80V

UTIL_5V0

0x1C

5.00V

UTIL_3V3

0x1D

3.30V

UTIL_2V5

0x1A

2.50V

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Содержание Kintex UltraScale FPGA KCU1250

Страница 1: ...KCU1250 Board User Guide UG1057 v1 0 December 19 2014...

Страница 2: ...1250 User Guide www xilinx com 2 UG1057 v1 0 December 19 2014 Revision History The following table shows the revision history for this document Date Version Revision 12 19 2014 1 0 Initial Xilinx rele...

Страница 3: ...ts 24 SuperClock 2 Module 24 User LEDs Active High 25 User DIP Switches Active High and I O Header 26 User Push Buttons Active High 27 MGT Transceivers and Reference Clocks 28 FPGA Mezzanine Card HPC...

Страница 4: ...Regulatory and Compliance Information Overview 76 Declaration of Conformity 76 Directives 76 Standards 76 Markings 77 Appendix F Additional Resources and Legal Notices Xilinx Resources 78 Solution Ce...

Страница 5: ...Kintex UltraScale device densities XCKU035 XCKU060 and XCKU075 in the pin compatible FFVA1156 package However certain GTH transceivers that are available in larger density devices are not available in...

Страница 6: ...board block diagram is shown in Figure 1 1 X Ref Target Figure 1 1 Figure 1 1 KCU1250 Board Block Diagram 3RZHU Q 9 RDUG 8WLOLW 3RZHU 2Q RDUG 3RZHU 5HJXODWLRQ 9 9 9 0 7 7UDQVFHLYHUV 48 48 48 48 48 48...

Страница 7: ...sections CAUTION The KCU1250 board can be damaged by electrostatic discharge ESD Follow standard ESD prevention measures when handling the board CAUTION Do not remove the rubber feet from the board T...

Страница 8: ...module page 24 11 U42 300 MHz LVDS oscillator page 23 12 DS17 FPGA DONE status LED page 25 13 DS3 FPGA INIT status LED page 25 14 SW7 FPGA PROGRAM pushbutton page 27 15 DS18 12V system power status L...

Страница 9: ...e to power it from a PC ATX power supply connector 12V power can also be provided through Connector J73 callout 31 Figure 1 2 which accepts an ATX hard drive 4 pin power plug Connector J27 callout 18...

Страница 10: ...wer switch FDS6681Z reference designator Q1 that is rated for 20A 12V It is critical that the power consumed by the DUT and peripheral circuitry does not exceed this limit Power Switch The KCU1250 boa...

Страница 11: ...gure 1 3 Figure 1 3 KCU1250 Board Power Supply Block Diagram 0D LP 8 9 DW PD 0 7 3RZHU 0RGXOH 0D LP 8 9 DW PD 0D LP 8 9 DW PD 0D LP 8 9 DW PD 0D LP 8 9 DW PD 0D LP 8 9 DW PD 0D LP 8 9 DW PD 0D LP 8 9...

Страница 12: ...P 1 8V Maxim MAX15301 U28 InTune Digital Point of Load PoL Controller 4A VCCO_HR 1 8V Utility Maxim MAX15301 U31 InTune Digital Point of Load PoL Controller 10A UTIL_5V0 5 0V Maxim MAX15301 U30 InTune...

Страница 13: ...can damage the board Each onboard FPGA logic regulator can be disabled using its respective power regulation inhibitor dip switch callout 17 Figure 1 2 A regulator is disabled when the power regulatio...

Страница 14: ...oring Data Menu in Appendix D The KCU1250 board includes these PMBus connectors J21 callout 20 Figure 1 2 for use with the Maxim USB to PMBus interface dongle MAXPOWERTOOL002 Ref 8 and the InTune Digi...

Страница 15: ...46 and J124 on the outlined and labeled power module locations shown in Figure 1 5 Table 1 4 lists the nominal voltage values for MGTAVCC MGTAVTT and MGTVCCAUX power rails It also lists the maximum cu...

Страница 16: ...Operation Active Heatsink Power Connector An active heat sink Figure 1 6 is provided for the FPGA callout 23 Figure 1 2 A 12V fan is affixed to the heat sink and is powered from the 3 pin friction lo...

Страница 17: ...Operation The fan power connections are detailed in Table 1 6 Figure 1 7 shows the heat sink fan power connector J99 Table 1 5 Fan Power Connections Fan Wire Header Pin Black J99 1 GND Red J99 2 12V...

Страница 18: ...ector callout 6 Figure 1 2 SD card using the Zynq 7000 AP SoC system controller in 8 bit SelectMAP mode callout 7 Figure 1 2 The KCU1250 board includes an embedded USB to JTAG configuration module Dig...

Страница 19: ...eiver U69 SN74AVC8T245 and adds the FMC interfaces to the chain PROGRAM Pushbutton Pressing the PROGRAM pushbutton SW7 callout 14 Figure 1 2 asserts the active Low program pin of the FPGA X Ref Target...

Страница 20: ...SoC U38 callout 33 Figure D 1 system controller that can be used to Configure the FPGA using predefined selection of configuration bit files on an SD card using 8 bit SelectMAP configuration Select t...

Страница 21: ...BLE bit switch position 1 is used to enable the SD card configuration mode The switch settings for selecting each address are shown in Table 1 6 X Ref Target Figure 1 9 Figure 1 9 Configuration DIP Sw...

Страница 22: ...ication terminal connection 115200 8 N 1 using the standard communication port of the Silicon Labs USB to dual UART bridge using four signal pins Transmit TX Receive RX Request to send RTS Clear to se...

Страница 23: ...or Table 1 7 FPGA to UART Connection FPGA U1 Schematic Net Name Device U32 Pin Function Direction IOSTANDARD Pin Function Direction D14 RTS Output LVCMOS18 UART_CTS_I_B 18 CTS Input C14 CTS Input LVCM...

Страница 24: ...power to the clock module interface Table 1 10 Differential SMA Clock Connections FPGA U1 Schematic Net Name SMA Connector Pin Function Direction IOSTANDARD G10 USER CLOCK_1_P Input LVDS CLK_DIFF_1_P...

Страница 25: ...l I O Output LVCMOS18 CM_C2A 91 C2A Input AM21 Control I O Output LVCMOS18 CM_H_CS0_C3A 95 CS0_C3A Input AN21 Control I O Output LVCMOS18 CM_H_CS1_C4A 97 CS1_C4A Input AL24 CM_RESET Output LVCMOS18 CM...

Страница 26: ...connected to the onboard system controller as additional GPIO between the two devices IMPORTANT Install J7 to connect the user DIP switches to the system controller Table 1 13 User DIP Switches FPGA...

Страница 27: ...buttons that are connected to user I O pins on the FPGA as shown in Table 1 14 These switches can be used for any function X Ref Target Figure 1 11 Figure 1 11 User I O J95 Table 1 14 User Push Button...

Страница 28: ...ock pins of the XCKU040 FPGA as shown in Figure 1 12 The MGT transceivers are grouped into five sets of four RX TX lanes referred to as a quad Q224 Q228 IMPORTANT Figure 1 12 is for reference only and...

Страница 29: ...ceiver pin is shown in Table 1 15 X Ref Target Figure 1 13 Figure 1 13 A MGT Connector Pad B MGT Connector Pinout Table 1 15 GTH Transceiver Pins U1 FPGA Pin Net Name Quad Connector Trace Length mils...

Страница 30: ...2 G29 132_TX1_P 132 J38 2943 4 D32 132_TX2_N 132 J38 2970 0 D31 132_TX2_P 132 J38 2970 6 B32 132_TX3_N 132 J38 2746 8 B31 132_TX3_P 132 J38 2748 8 AP1 224_RX0_N 224 J39 3318 6 AP2 224_RX0_P 224 J39 33...

Страница 31: ...40 2588 2 AC3 225_TX3_N 225 J40 2829 1 AC4 225_TX3_P 225 J40 2828 1 Y1 226_RX0_N 226 J41 2715 2 Y2 226_RX0_P 226 J41 2715 8 V1 226_RX1_N 226 J41 2218 3 V2 226_RX1_P 226 J41 2218 7 T1 226_RX2_N 226 J41...

Страница 32: ...48 5 G3 227_TX3_N 227 J42 2940 4 G4 227_TX3_P 227 J42 2939 5 E3 228_RX0_N 228 J43 3117 4 E4 228_RX0_P 228 J43 3118 0 D1 228_RX1_N 228 J43 2521 3 D2 228_RX1_P 228 J43 2522 0 B1 228_RX2_N 228 J43 2601 5...

Страница 33: ...J38 L29 132_REFCLK0_P 225 J38 J30 132_REFCLK1_N 225 J38 J29 132_REFCLK1_P 225 J38 AF5 224_REFCLK0_N 226 J39 AF6 224_REFCLK0_P 226 J39 AD5 224_REFCLK1_N 226 J39 AD6 224_REFCLK1_P 226 J39 AB5 225_REFCLK...

Страница 34: ...FMC Connector Pinouts for a cross reference of signal names to pin coordinates The FMC1 HPC connector JA2 provides connectivity for 43 differential user defined pairs 34 LA pairs 9 HA pairs 4 differe...

Страница 35: ...CLK0_M2C_N H5 E22 FMC1_CLK1_M2C_P G2 E23 FMC1_CLK1_M2C_N G3 G10 FMC1_CLK2_BIDIR_P K4 F10 FMC1_CLK2_BIDIR_N K5 G9 FMC1_CLK3_BIDIR_P J2 F9 FMC1_CLK3_BIDIR_N J3 D24 FMC1_HA00_CC_P F4 C24 FMC1_HA00_CC_N F...

Страница 36: ...FMC1_LA09P D14 K13 FMC1_LA09N D15 K11 FMC1_LA10P C14 J11 FMC1_LA10N C15 K10 FMC1_LA11P H16 J10 FMC1_LA11N H17 J9 FMC1_LA12P G15 H9 FMC1_LA12N G16 L8 FMC1_LA13P D17 K8 FMC1_LA13N D18 E10 FMC1_LA14P C1...

Страница 37: ...LA24N H29 B20 FMC1_LA25P G27 A20 FMC1_LA25N G28 C22 FMC1_LA26P D26 C21 FMC1_LA26N D27 B22 FMC1_LA27P C26 B21 FMC1_LA27N C27 B24 FMC1_LA28P H31 A24 FMC1_LA28N H32 C26 FMC1_LA29P G30 B26 FMC1_LA29N G31...

Страница 38: ...7 FMC2_HA00_CC_N F5 AV18 FMC2_HA01_CC_P E2 AW18 FMC2_HA01_CC_N E3 BC18 FMC2_HA02P K7 BD18 FMC2_HA02N K8 BD16 FMC2_HA03P J6 BD15 FMC2_HA03N J7 BC19 FMC2_HA04P F7 BD19 FMC2_HA04N F8 AN13 FMC2_HA05P E6 A...

Страница 39: ...FMC2_LA10N C15 AE8 FMC2_LA11P H16 AF8 FMC2_LA11N H17 AD11 FMC2_LA12P G15 AE11 FMC2_LA12N G16 AE12 FMC2_LA13P D17 AF12 FMC2_LA13N D18 AH13 FMC2_LA14P C18 AJ13 FMC2_LA14N C19 AE13 FMC2_LA15P H19 AF13 FM...

Страница 40: ...G27 T25 FMC2_LA25N G28 T27 FMC2_LA26P D26 R27 FMC2_LA26N D27 L22 FMC2_LA27P C26 K23 FMC2_LA27N C27 L25 FMC2_LA28P H31 K25 FMC2_LA28N H32 L23 FMC2_LA29P G30 L24 FMC2_LA29N G31 M27 FMC2_LA30P H34 L27 FM...

Страница 41: ...FMC3_HA00_CC_N F5 AC31 FMC3_HA01_CC_P E2 AC32 FMC3_HA01_CC_N E3 AA27 FMC3_HA02P K7 AB27 FMC3_HA02N K8 AC26 FMC3_HA03P J6 AC27 FMC3_HA03N J7 AB24 FMC3_HA04P F7 AC24 FMC3_HA04N F8 AD25 FMC3_HA05P E6 AD...

Страница 42: ...9N D15 V22 FMC3_LA10P C14 V23 FMC3_LA10N C15 U21 FMC3_LA11P H16 U22 FMC3_LA11N H17 AB21 FMC3_LA12P G15 AC21 FMC3_LA12N G16 AA20 FMC3_LA13P D17 AB20 FMC3_LA13N D18 AC22 FMC3_LA14P C18 AC23 FMC3_LA14N C...

Страница 43: ...3_LA25P G27 AB34 FMC3_LA25N G28 AA29 FMC3_LA26P D26 AB29 FMC3_LA26N D27 AC34 FMC3_LA27P C26 AD34 FMC3_LA27N C27 AE33 FMC3_LA28P H31 AF34 FMC3_LA28N H32 AE32 FMC3_LA29P G30 AF32 FMC3_LA29N G31 AF33 FMC...

Страница 44: ...og inputs and an integrated analog to digital converter ADC The SYSMON is powered using the on chip reference voltage VREFP shown in Figure 1 14 More information about the system monitor is available...

Страница 45: ...tors and power monitoring SuperClock 2 module MGT power module FMC1 FMC2 FMC3 Table 1 20 shows the I2C channel assignments The upstream port of the TCA9548 multiplexer connects to PCA9306 U46 U53 U55...

Страница 46: ...peration X Ref Target Figure 1 15 Figure 1 15 I2C Bus Multiplexer and Upstream Repeater 3 75 XV 5HSHDWHU 6 VWHP RQWUROOHU 7 3 5 3 75 XV 5HSHDWHU 8OWUD6FDOH 3 30 XV 6XSHU ORFN 6 6B 53520 0 0 0 6 VWHP R...

Страница 47: ...ormal operation Table A 1 Default Jumper Settings Reference Designator Name Board Location Jumper Dip switch Position Comments SW2 1 VCCINT Lower left OFF SW2 2 VCCBRAM Lower left OFF SW2 3 VCCAUX Low...

Страница 48: ...er 19 2014 Appendix B VITA 57 1 FMC Connector Pinouts Introduction Figure B 1 provides a cross reference of signal names to pin coordinates for the VITA 57 1 FMC HPC connector X Ref Target Figure B 1...

Страница 49: ...operty IOSTANDARD LVCMOS18 get_ports FMC1_CLK0_M2C_P set_property PACKAGE_PIN G12 get_ports FMC1_CLK0_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_CLK0_M2C_N set_property PACKAGE_PIN E22 get_...

Страница 50: ..._ports FMC1_LA09N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA09N set_property PACKAGE_PIN K11 get_ports FMC1_LA10P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA10P set_property PACKAGE_PIN...

Страница 51: ...RD LVCMOS18 get_ports FMC1_LA24P set_property PACKAGE_PIN D21 get_ports FMC1_LA24N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA24N set_property PACKAGE_PIN B20 get_ports FMC1_LA25P set_property...

Страница 52: ...TANDARD LVCMOS18 get_ports FMC1_HA04P set_property PACKAGE_PIN E8 get_ports FMC1_HA04N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA04N set_property PACKAGE_PIN B29 get_ports FMC1_HA05P set_prope...

Страница 53: ...ts FMC2_LA06P set_property PACKAGE_PIN AP9 get_ports FMC2_LA06N set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA06N set_property PACKAGE_PIN AL10 get_ports FMC2_LA07P set_property IOSTANDARD LVCMOS1...

Страница 54: ...ty PACKAGE_PIN P20 get_ports FMC2_LA21P set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA21P set_property PACKAGE_PIN P21 get_ports FMC2_LA21N set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA21N se...

Страница 55: ...PIN N26 get_ports FMC2_HA01_CC_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA01_CC_N set_property PACKAGE_PIN AK12 get_ports FMC2_HA02P set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA02P set_...

Страница 56: ...get_ports FMC3_LA02N set_property PACKAGE_PIN V29 get_ports FMC3_LA03P set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA03P set_property PACKAGE_PIN W29 get_ports FMC3_LA03N set_property IOSTANDARD...

Страница 57: ...ts FMC3_LA17_CC_P set_property PACKAGE_PIN AB32 get_ports FMC3_LA17_CC_N set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA17_CC_N set_property PACKAGE_PIN AD30 get_ports FMC3_LA18_CC_P set_property I...

Страница 58: ...N set_property PACKAGE_PIN AF30 get_ports FMC3_LA32P set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA32P set_property PACKAGE_PIN AG30 get_ports FMC3_LA32N set_property IOSTANDARD LVCMOS18 get_ports...

Страница 59: ...PACKAGE_PIN AM24 get_ports CM_C2B set_property IOSTANDARD LVCMOS18 get_ports CM_C2B set_property PACKAGE_PIN AN24 get_ports CM_C3B set_property IOSTANDARD LVCMOS18 get_ports CM_C3B set_property PACKA...

Страница 60: ...operty PACKAGE_PIN D18 get_ports APP_LED1 set_property IOSTANDARD LVCMOS18 get_ports APP_LED1 set_property PACKAGE_PIN D19 get_ports APP_LED2 set_property IOSTANDARD LVCMOS18 get_ports APP_LED2 set_pr...

Страница 61: ...ts DUT_FREQ_RDY set_property IOSTANDARD LVCMOS18 get_ports DUT_FREQ_RDY UART set_property PACKAGE_PIN B14 get_ports UART_TXD_O set_property IOSTANDARD LVCMOS18 get_ports UART_TXD_O set_property PACKAG...

Страница 62: ...33 get_ports 132_RX0_P set_property PACKAGE_PIN G34 get_ports 132_RX0_N set_property PACKAGE_PIN AD6 get_ports 224_REFCLK1_P set_property PACKAGE_PIN AD5 get_ports 224_REFCLK1_N set_property PACKAGE_P...

Страница 63: ...E_PIN AA3 get_ports 226_TX0_N set_property PACKAGE_PIN Y2 get_ports 226_RX0_P set_property PACKAGE_PIN Y1 get_ports 226_RX0_N set_property PACKAGE_PIN M6 get_ports 227_REFCLK1_P set_property PACKAGE_P...

Страница 64: ...8_RX2_N set_property PACKAGE_PIN D6 get_ports 228_TX1_P set_property PACKAGE_PIN D5 get_ports 228_TX1_N set_property PACKAGE_PIN D2 get_ports 228_RX1_P set_property PACKAGE_PIN D1 get_ports 228_RX1_N...

Страница 65: ...ation port of the Silicon Labs USB to dual UART described in USB to Dual UART Bridge The main menu lists the available options KCU1250 System Controller Main Menu 1 Set Programmable Clocks 2 Get Power...

Страница 66: ...i570 Frequency Enter the Si570 frequency 10 810MHz 200 Enter a value between 10 and 810 Freq 200 0000000000 HS_DIV 7 N1 4 DCO 5600 0 RFREQ 0x030FFFF785 The returned values include diagnostic informati...

Страница 67: ...menu these power rails can be read once or scanned continuously until stopped by a key press Table D 1 lists the voltage rails accessible through the system controller s interface to the Maxim PMBus T...

Страница 68: ...V5 Voltage 0 Return to Main Menu Get PMBus Voltages VCCINT 0 950V VCCAUX 1 800V VCCBRAM 0 950V VCCO_HP 1 800V VCCO_HR 1 801V UTIL2V5 2 500V UTIL3V3 3 300V UTIL5V0 4 999V Continuous Scan PMBus Voltages...

Страница 69: ...diagnostic information Get VCCO_HR Voltage VCCO_HR 1 800V Unscaled Hex MSB 0x1C LSB 0xCD The returned values include diagnostic information Get UTIL5V0 Voltage UTIL5V0 5 000V Unscaled Hex MSB 0x50 LS...

Страница 70: ...and maximum current of each rail The list is updated about once per second Pressing any key displays the PMBus menu Advanced INA226 Setting This option can be used to select one of the PMBus power mon...

Страница 71: ...ster 4 Set CONFIGURATION Register 0 Return to Previous Menu FPGA Mezzanine Card Menu The KCU1250 board includes three FPGA mezzanine card FMC ANSI VITA 57 1 expansion interfaces All FMC cards must hos...

Страница 72: ...to Main Menu Identify the FMC module type s and the FMC connecter number These examples use FMC XM107 connected to FMC1 Set FMC XMxxx Clocks KCU1250 System Controller FMC Clock Menu 1 Set FMC XM101 C...

Страница 73: ...7 Enter the Si570 frequency 10 810MHz 100 Freq 100 0000000000 HS_DIV 5 N1 10 DCO 5000 0 RFREQ 0x02BC7E566E The returned values include diagnostic information Read FMC IIC EEPROM If the FMC IIC EEPROM...

Страница 74: ...n GPIO Readings 0 Return to Main Menu Select an option Get GPIO PL Data The signals monitored with this option are currently not available in the KCU1250 board FMC1_PRSNT NO FMC2_PRSNT NO PMBUS_CABLE_...

Страница 75: ...ller mode DIP switch SW13 see System Controller Configuration DIP Switches CONFIG Menu Options KCU1250 System Controller CONFIG Menu 1 Configure UltraScale FPGA from SD Card 0 Return to Main Menu Conf...

Страница 76: ...he CE requirements for the PC Test Environment Master Answer Record Xilinx AR63058 Declaration of Conformity The Kintex UltraScale KCU1250 Declaration of Conformity will be made available online Direc...

Страница 77: ...te measures Safety IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements EN 60950 1 2006 Information technology equipment Safety Part 1 General requirements Markings Thi...

Страница 78: ...troubleshooting tips References The most up to date information related to the KCU1250 board and its documentation is available on these websites KCU1250 Characterization Kit KCU1250 Characterization...

Страница 79: ...a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correc...

Страница 80: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Xilinx CK U1 KCU1250 G...

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