Xilinx Kintex UltraScale FPGA KCU1250, Руководство пользователя

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KCU1250 User Guide www.xilinx.com 23
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
The driver assigns the higher PC COM port number to UART1 (SCI) and the lower PC COM
port number to UART(ECI).
The connections of these signals between the FPGA and the Silicon Labs CP2105 are listed
in Table 1-7 .
The bridge device also provides as many as four GPIO signals that you can define for status
and control information ( Table 1-8 ).
The second port of the CP2105 USB to dual-UART is connected to the onboard system
controller. See Appendix D, System Controller .
300 MHz LVDS Oscillator
The KCU1250 board has one 300 MHz LVDS oscillator U42 (callout 11, Figure 1-2 )
connected to multi-region clock capable (MRCC) inputs on the FPGA. Table 1-9 lists the
FPGA pin connections to the LVDS oscillator.
Table 1-7: FPGA to UART Connection
FPGA(U1)
Schematic Net
Name
Device(U32)
Pin Function Direction IOSTANDARD Pin Function Direction
D14 RTS Output LVCMOS18 UART_CTS_I_B 18 CTS Input
C14 CTS Input LVCMOS18 UART_RTS_O_B 19 RTS Output
A14 TX Output LVCMOS18 UART_RXD_I 20 RXD Input
B14 RX Input LVCMOS18 UART_TXD_O 21 TXD Output
Table 1-8: CP2105 USB to Dual-UART Bridge User GPIO
FPGA(U1) Schematic Net
Name
Device(U32)
Pin Function Direction IOSTANDARD Pin Function Direction
F14 SelectIO™ In/Out LVCMOS18 UART_GPIO_0 24 GPIO In/Out
G14 SelectIO In/Out LVCMOS18 UART_GPIO_1 23 GPIO In/Out
J14 SelectIO In/Out LVCMOS18 UART_GPIO_2 22 GPIO In/Out
J15 SelectIO In/Out LVCMOS18 UART_GPIO_3 15 GPIO In/Out
Table 1-9: 10 LVDS Oscillator MRCC Connections
FPGA (U1)
Schematic
Net Name
Device (42)
Pin Function Direction
I/O
Standard
Pin Function Direction
E18 SYSTEM CLOCK_P Input LVDS LVDS_OSC_P 4 300 MHz LVDS oscillator Output
E17 SYSTEM CLOCK_N Input LVDS LVDS_OSC_N 5 300 MHz LVDS oscillator Output
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