KCU1250 User Guide
24
UG1057 (v1.0) December 19, 2014
Chapter 1:
KCU1250 Board Features and Operation
Differential SMA MRCC Pin Inputs
The KCU1250 board provides two pairs of differential SMA transceiver clock inputs (callout
32,
) that can be used for connecting to an external clock source. The FPGA MRCC
pins are connected to the SMA connectors as shown in
SuperClock-2 Module
The SuperClock-2 module (callout 10,
) connects to the clock module interface
connector (J36) and provides a programmable, low-noise and low-jitter clock source for the
KCU1250 board (see
SuperClock-2 Module User Guide
(UG770)
). The clock module
maps to FPGA I/O by way of 14 control pins, 2 LVDS pairs, 1 regional clock pair, and 1 reset
pin.
shows the FPGA I/O mapping for the SuperClock-2 module interface. The
KCU1250 board supplies UTIL_5V0, UTIL_3V3, UTIL_2V5, and V
CCO_HP
input power to the
clock module interface.
Table 1-10:
Differential SMA Clock Connections
FPGA(U1)
Schematic Net
Name
SMA
Connector
Pin
Function
Direction
IOSTANDARD
G10
USER CLOCK_1_P
Input
LVDS
CLK_DIFF_1_P
J84
F10
USER CLOCK_1_N
Input
LVDS
CLK_DIFF_1_N
J85
G9
USER CLOCK_2_P
Input
LVDS
CLK_DIFF_2_P
J83
F9
USER CLOCK_2_N
Input
LVDS
CLK_DIFF_2_N
J86
Table 1-11:
SuperClock-2 FPGA I/O Mapping
FPGA(U1)
Schematic Net
Name
J36 Pin
Pin
Function
Direction IOSTANDARD
Pin
Function
Direction
U34
Clock recovery
Input
LVDS
CM_LVDS1_P
1
Clock recovery
Output
V34
Clock recovery
Input
LVDS
CM_LVDS1_N
3
Clock recovery
Output
J8
Clock recovery
Input
LVDS
CM_LVDS2_P
9
Clock recovery
Output
H8
Clock recovery
Input
LVDS
CM_LVDS2_N
11
Clock recovery
Output
AK22
Regional clock
Input
LVDS
CM_GCLK_P
25
Global clock
Output
AK23
Regional clock
Input
LVDS
CM_GCLK_N
27
Global clock
Output
AN23
Control I/O
Output
LVCMOS18
CM_H_DEC
67
DEC
Input
AP23
Control I/O
Output
LVCMOS18
CM_H_INC
69
INC
Input
AP24
Control I/O
Output
LVCMOS18
CM_FS_ALIGN
71
ALIGN
Input
AP25
Control I/O
Input
LVCMOS18
CM_H_LOL
79
LOL
Output
