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SMP7500 Theory of Operation
61
The F/P CLK inputs from the UUT are terminated in the SMP7500 by a RC network of 120
Ω
to
ground through a 100 pF capacitor and a 47 k
Ω
resistor to VCC. This termination value gives a
time constant of 12 ns for fast rise times on input clocks, and will not load the UUT driving
source.
L
ATCH
D
ATA
The selected edge of the selected Input Clock signal/event then clocks the I/O Data Buffer to read
data from the UUT. The selected Input Clock signal may also be set to generate a trigger signal to
the VXI backplane TTLT Bus, thereby signaling incoming data from the UUT.
R
EAD
D
ATA
A read of the appropriate PORT register will now yield the data that was latched in from the UUT.
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