VXI Technology SMP7500, Руководство пользователя

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40 SMP7500 Programming
CONTROL REGISTER F/P CLK SELECT – Read and Write
D2-D0
F/P CLK Select for
PORTs 5 thru 0
Value Clock selected
0 GND
1
F/P CLK 0
2 F/P CLK 1
3 F/P CLK 2
4 F/P CLK 3
5 F/P CLK 4
6 F/P CLK 5
7 Relay Register Write Event MUX
For Ports 5 thru 0, these bits select the F/P CLK Lines 5 thru 0 that
become the “F/P CLK Select MUX” output. This output may then be
selected to drive the various Port clocks 5 thru 0 in the system. Note
that if a Port F/P CLK other than 5 thru 0 is desired to be used as a
clock source for Ports 5 thru 0, then the Global CLK hardware
jumpers on the board should be utilized to connect the desired F/P
CLK signal to the Global CLK, and then on to the proper PORT
CLK as desired.
Pon state = 0
D7-D3 Unused These bits are unused.
D10-D8
F/P CLK Select for
PORTs 11 thru 6
Value Clock selected
0 GND
1
F/P CLK 6
2 F/P CLK 7
3 F/P CLK 8
4 F/P CLK 9
5 F/P CLK 10
6 F/P CLK 11
7 Relay Register Write Event MUX
For Ports 11 thru 6, these bits select the F/P CLK Lines 11 thru 6 that
become the “F/P CLK Select MUX” output. This output may then be
selected to drive the various Port clocks 11 thru 6 in the system. Note
that if a Port F/P CLK other than 11 thru 6 is desired to be used as a
clock source for Ports 11 thru 6, then the Global CLK Jumpers on
the board should be utilized to connect the desired F/P CLK signal to
the Global CLK, and then on to the proper Port CLK as desired.
Pon state = 0
D15-D11 Unused These bits are unused.
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