VXI Technology, Inc.
38
SMP7500 Programming
CONTROL REGISTER PORT 11 thru 0 (Continued) – Read and Write
D8
PORT Output Clock
Polarity Select
Set to 0 for non-inverted Output Clock operation.
Set to 1 for inverted Output Clock operation.
Pon state = 0
D9
PORT Output Clock
Enable
Set to 0 to disable Output Clock generation.
Set to 1 to enable Output Clock generation.
Pon state = 0
D11-D10
PORT Clock to Input Port
Select
Value: Clock
selected:
0
F/P CLK 11/0 respectively
1
Relay Register Write Event MUX
2
Relay Register 000Ch Write Event
3
F/P CLK Select MUX
Pon state = 0
D12
PORT Clock to Input
PORT Polarity Select
Set to 0 for non-inverted Clock to Input Port operation.
Set to 1 for inverted Clock to Input Port operation.
Pon state = 0
D13
PORT Input Clock Select
Set to 0 to select asynchronous input Port operation
Set to 1 to select synchronous input Port operation.
Pon state = 0
D15-D14
Unused
A write to these bits has no effect.
CONTROL REGISTER F/P OVER CURRENT SENSE - Read
D15-D0
Over Current Sense Lines
[15:0] Read Back
The SMP7500 has 16 separate over current sense circuits. This is due
to the nature of the output drivers that are used on the module. They
are portioned by 6, and not by 8 like the PORTs themselves. A read
back of this register is a direct read back of the hardware over
current sense circuits. The non-Over Current state of these bits is 0.
Pon state = Dependent
CONTROL REGISTER LATCHED OVER CURRENT SENSE - Read
D15-D0
Latched Over Current
Sense Lines [15:0] Read
Back
The SMP7500 has 16 separate over current sense circuits. This is due
to the nature of the output drivers that are used on the module. They
are portioned by 6, and not by 8 like the PORTs themselves. A read
back of this register is a read back of a latched version of the over
current sense circuits.
These bits are set to 1 by an over current occurrence. They will
remain set until reset by the corresponding Over Current Reset bit.
The non-Over Current state of these bits is 0.
Pon state = Dependent
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