VXI Technology, Inc.
62
SMP7500 Index
I
NDEX
A
A16 address space ..........................................................................27
A16 Base Address ..........................................................................25
A16 Offset Register........................................................................25
A16 Offset Register Address .........................................................25
A24 address space ..........................................................................25
A24 Base Address ..........................................................................25
A24/A32 Active .............................................................................27
A24/A32 Enable .............................................................................27
A24/A32 Memory Offset ...............................................................28
A32 address space ..........................................................................25
A32 Base Address ..........................................................................25
ACCESS/ERROR ..........................................................................12
address space ..................................................................................19
Address Space ................................................................................27
address space allocation .................................................................25
asynchronous ............................................................................38, 47
B
backplane jumpers..........................................................................17
Binary numbers ..............................................................................53
buffered ..............................................................................37, 44, 45
buffers.......................................................................................55, 56
bus interface .............................................................................35, 51
Busy signal .........................................................................28, 41, 42
C
Cause/Status ...................................................................................28
channels ....................................................................... 12, 13, 21, 55
circuits ............................................................................................38
CLK0-5...........................................................................................53
Clock Enable ......................................................... 38, 47, 49, 56, 59
clock line ........................................................................................58
Clocked Mode ................................................................................53
command parsing ...........................................................................25
connector ........................................................................................20
connector style................................................................................20
Control Register Map .....................................................................35
cooling ............................................................................................17
current........................................................ 12, 13, 15, 30, 38, 39, 51
Current in........................................................................................15
Current sink ....................................................................................15
D
Data Input .......................................................................................12
data line ....................................................................................21, 22
Data Load .......................................................................................56
data written .........................................................................32, 50, 53
Delay Timer........................................................................35, 41, 42
Device Class ...................................................................................27
Device transfers........................................................................56, 59
Device triggering............................................................................58
Digital I/O Module .............................................................17, 35, 51
drivers .............................................................................................38
dynamic configuration....................................................................27
E
Event MUX ........................................................... 37, 38, 40, 41, 42
Extended Memory ..............................................................19, 29, 35
Extended Memory Device..............................................................29
Extended Memory Space ............................................................... 19
external connector .......................................................................... 53
F
FAIL/POWER................................................................................ 12
Firmware Version Number ............................................................ 28
Front Panel .............................................................12, 15, 20, 21, 22
front panel connector ...................................................55, 56, 58, 59
G
Global Clock Line.......................................................................... 13
H
Handler IRQ Line........................................................................... 29
hardware ...............................................13, 21, 22, 25, 28, 38, 39, 40
Hexadecimal numbers.................................................................... 53
I
IH ENA* ........................................................................................ 29
IMMEDIATE................................................................................. 53
incoming data ................................................................................. 61
input clocks ..............................................................................53, 61
Input impedance ............................................................................. 15
input line ........................................................................................ 21
Interrupt Mask................................................................................ 29
Interrupter IRQ Line ...................................................................... 29
inverted Clock ..............................................................38, 41, 42, 47
IR ENA*......................................................................................... 29
IRQ line .......................................................................................... 29
J
jumpers .........................................................................13, 21, 22, 40
L
Latch Data ...................................................................................... 61
logical address..............................................................17, 18, 19, 27
Logical Address .......................................................................25, 27
LSB
least significant bit .............................................................18, 19
M
Major Hardware Version Number ................................................. 28
Manufacturer's ID .......................................................................... 27
Memory Map......................................................................25, 35, 51
message-based................................................................................ 25
Minor Hardware Version Number ................................................. 28
Model Code.................................................................................... 27
MODID* ........................................................................................ 27
MSB
most significant bit.............................................................18, 19
N
N-DMOS ........................................................................................ 12
O
Octal numbers ................................................................................ 53
offset.........................................................................................25, 51
Offset Register ............................................................................... 25
offset value ..................................................................................... 25
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