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Issued June 20, 2007 M5000 Series: User Guide
Mercury PXB++ PCI-to-RACE++ Bridge
5.4 Mercury PXB++ PCI-to-RACE++ Bridge
The PXB++ implements the functions required to bridge the PCI local bus with the RACEway
Interlink crossbar fabric. The PXB++ performs all necessary address translation and routing
functions to support high speed transfers between the local PCI bus and either native RACEway
interfaces or remote PCI buses which also use PXB++ interfaces.
This architecture allows PXB++ to be used for two distinct types of applications. In the first type of
application, the PXB++ is used as an interface technology to RACEway to support I/O interfaces
between industry-standard devices and native RACEway processing elements. This application
allows the RACEway designer to use PXB++ to gain access to the wide range of off-the-shelf
interface devices which are available for the PCI local bus.
In the second type of application, the PXB++ is used to implement a transparent PCI-to-PCI bridge
through the RACEway fabric. In this application, the PCI system designer uses the PXB++ and
RACEway technology to create PCI-to-PCI scalable bandwidth without implementing native
RACEway processing. By implementing a transparent Plug & Play PCI bridge, the PXB++ can
make RACEway technology accessible without requiring "RACEway awareness" at the PCI bus
level.
The design and basic functionality of the PXB++ are the same for both application types. The
differences are primarily in initial configuration and in the control software's viewpoint of the
PXB++ device.
Power-up / Reset Configuration
PCI Reset Control
Enable or disable PXB++ reset from PCI using Jumper JP1. See “PCI-to-RACEway Bridge Reset”
on page 17.
EEPROM
At boot-up, an external EEPROM is used by the PXB++ to initialize its internal registers.
Enable or disable (default configuration) the auto-load process usingDIP switch SW7. See “PCI to
RACEway Bridge” on page 16. Data is downloaded from address 0.