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Issued June 20, 2007

M5000 Series: User Guide

PCI Slave Images

PCI Slave Image 2

PCI Slave Image 2 is set up to map PCI Memory Space transactions, in the address range
0x4000.0000-0x5FFF.FFFF to A32, D64 VMEbus cycles, in the address range 0x0000.0000-
0x1FFF.FFFF.

1) This column shows write data for configuration from PCI

Initialization Sequence

By performing the list of cycles shown in the table below, the mapping for this configuration
example is achieved.

1) This column shows write data for configuration from PCI

TABLE B-8.

PCI slave image 2 setup

Write from VME

PCI Data 1)

Result:

D:0x0000.0040 to A:0x00012C

0x4000.0000

Base Address set to 0x4000.0000

D:0x0000.0060 to A:0x000130

0x6000.0000

Bound Address set to 0x6000.0000

D:0x0000.00C0 to A:0x000134

0xC000.0000

Translation Offset set to 0xC000.0000

D:0x0001.C2C0 to A:0x000128

0xC0C2.0100

Enable Image, VAS=A32, VDW=D64, LAS=Mem.
Space, PGM=data, SUPER=non-priv, Posted Write
enabled, BLT allowed.

TABLE B-9.

Initialization sequence for PCI slave image config. example.

Write from VME

PCI Data 1)

Result:

D:0x0700.8002 to A:0x000004

0x0200.0007

PCI Target Enable bits set. (this write cycle also sets the PCI master
enable bit if it is disabled, ref. VMEbus Slave Image section).

D:0x0000.0000 to A:0x000104

0x0000.0000

LSI_0: Base Address set to 0x0000.0000

D:0x0010.0000 to A:0x000108

0x0000.1000

LSI_0: Bound Address set to 0x0000.1000

D:0x0010.0000 to A:0x00010C

0x0000.1000

LSI_0: Translation Offset set to 0x0000.1000

D:0x0110.4180 to A:0x000100

0x8041.1001

LSI_0: Enable Image, VAS=A24, VDW=D16, LAS=I/O Space,
PGM=data, SUPER=supervisor, other options disabled.

D:0x0000.0010 to A:0x000118

0x1000.0000

LSI_1: Base Address set to 0x1000.0000

D:0x0000.0030 to A:0x00011C

0x3000.0000

LSI_1: Bound Address set to 0x3000.0000

D:0x0000.0010 to A:0x000120

0x1000.0000

LSI_1: Translation Offset set to 0x1000.0000

D:0x0001.82C0 to A:0x000114

0xC082.0100

LSI_1: Enable Image, VAS=A32, VDW=D32, LAS=Mem. Space,
PGM=data, SUPER=non-priv, Posted Write enabled, BLT allowed.

D:0x0000.0040 to A:0x00012C

0x4000.0000

LSI_2: Base Address set to 0x4000.0000

D:0x0000.0060 to A:0x000130

0x6000.0000

LSI_2: Bound Address set to 0x6000.0000

D:0x0000.00C0 to A:0x000134

0xC000.0000

LSI_2: Translation Offset set to 0xC000.0000

D:0x0001.C2C0 to A:0x000128

0xC0C2.0100

LSI_2: Enable Image, VAS=A32, VDW=D64, LAS=Mem. Space,
PGM=data, SUPER=non-priv, Posted Write enabled, BLT allowed.

Содержание M5210RP-EFF

Страница 1: ...User Guide Power MIDAS M5000 Series Single Board Computer...

Страница 2: ...are and Firmware code provided by VMETRO described herein is proprietary to VMETRO or its licensors The use of this Software and Firmware is governed by a licensing agreement included on the media on...

Страница 3: ...miss use or accident or for products that have failed or malfunctioned after the expiry of the warranty the costs of repair or replacement will not be covered by VMETRO VMETRO specifically disclaims a...

Страница 4: ...RO Pte Ltd 175A Bencoolen Street 06 09 Burlington Square Singapore 189650 Phone 65 6238 6010 Fax 65 6238 6020 info vmetro com sg Nordic Baltic Countries VSYSTEMS AB Drottninggatan 104 SE 111 60 Stockh...

Страница 5: ...m surrounding Processor PMC Subsystem Extension Subsystem Miscellaneous Functions information on JTAG Chain Reset Network Interrupt Routing Power Supplies Mezzanine PMC Carrier Explains how to install...

Страница 6: ...you have any comments or feedback with respect to our products and services please feel free to contact us through the support channels listed here or email us at comments vmetro no Technical Support...

Страница 7: ...in 10 Precautions in Handling and Storage 10 Inspection 10 2 2 Installing PMC Modules 11 Mounting of PMC modules 1 and 2 on the M52xx board 11 2 3 Switches and Jumper Settings 12 Default Jumper and Sw...

Страница 8: ...to PCI X Bridges 32 Power up Reset Configuration Options 32 Primary Interface 32 Secondary Interface 33 4PMC Subsystem 35 4 1 Introduction 36 PMC Power 36 4 2 Secondary and Tertiary PCI Segments 37 PC...

Страница 9: ...MC Modules onto the PMC Carrier 52 PMC Carrier Daisy Chain 54 6 4 Functional Description 55 System Overview 55 Arbitration on the mezzanine bus 55 IDSEL generation 55 Interrupt routing 56 Debug Functi...

Страница 10: ...nector Pinout 95 General Description 96 VME P0 Connector for all models 97 VME P1 Connector for all models 99 VME P2 Connector for non R model 100 VME P2 Connector for R models 101 EPMC Connector Pino...

Страница 11: ...ocessor Subsystem Block Diagram 26 FIGURE 3 2 LEDs on the MDC RJ45 I O spacer 28 FIGURE 3 3 AMCC 440GX I2C Devices 30 FIGURE 4 1 PMC Subsystem Block Diagram 36 FIGURE 5 1 Extension Subsystem 42 FIGURE...

Страница 12: ...xii M5000 Series User Guide Issued June 20 2007 5 23...

Страница 13: ...r Consumption 19 TABLE 2 11 Environmental Specifications for the M5000 and C5000Series 20 TABLE 2 12 Fibre Channel Port LEDS 22 TABLE 3 1 Ethernet LEDs for EMAC0 28 TABLE 3 2 Ethernet LEDs on the MDC...

Страница 14: ...4 configuration ROM 90 TABLE C 2 CR Entry Board ID Offset 0x00033 0x0003F 91 TABLE C 4 CR Entry Revision ID Offset 0x00043 0x0004F 92 TABLE C 3 Assigned Board ID Values 92 TABLE C 5 Revision ID Descri...

Страница 15: ...s is part of the next generation of boards in the MIDAS family As for the previous generations the M5000 series focuses on high performance data buffering and flexible data flows between I O ports I O...

Страница 16: ...tor thus adding up to 3 Ethernet ports One Fast Ethernet 10 100 SMII and two Gigabit Ethernet 10 100 1000 RGMII and an I2C bus Note Adding more than one Gigabit Ethernet port will reduce the number of...

Страница 17: ...ps Ethernet connections and two serial connections RS 232 or RS 422 Additionally the AMCC 440GX processor provides simple connectivity of additional peripheral devices through an external local bus Th...

Страница 18: ...channel Fibre Channel processor which connects the 64 bit 133MHz PCI X bus to one or two 2 Gib Fibre Channel Fabrics or loops PCI boot configuration is stored into an SPROM two SRAMs one per channel...

Страница 19: ...ower supply 3A Max current per PMC for 5V power supply 3A Max current per PMC for V I O power supply 2A Additional Connections Additionally to the standard PCI X buses the PMC sites include the follow...

Страница 20: ...rd Interrupt Routing The components on the M5000 board provide several interrupt sources and destinations The primary interrupt destination is the AMCC 440GX processor but interrupts may also be route...

Страница 21: ...atible with the tools connector For more information please contact VMETRO Temperature Sensors Temperature sensors are very useful when monitoring applications during extreme conditions Several temper...

Страница 22: ...8 M5000 Series User Guide Issued June 20 2007 Product Overview...

Страница 23: ...9 M5000 Series User Guide Issued June 20 2007 2 Installation and Hardware description...

Страница 24: ...urfaces with controlled static characteristics i e specially designed anti static table covers When handing the board to another person first touch this person s hand wrist etc to discharge any static...

Страница 25: ...000 board on a smooth static protected work surface 2 Install PMC module 2 in the upper PMC position 3 Install PMC module 1 in the lower PMC position 4 Secure PMC modules with screws on the bottom sid...

Страница 26: ...ME Settings SW6 PMC Monarch Selection SW7 RACEway to VME bridge settings SW10 Processor Subsystem settings SW11 PCI to VME bridge settings SW2 PCI X to PCI X Bridge 1 SW9 PCI X to PCI X Bridge 2 JP2 W...

Страница 27: ...2 1 Default Jumper and Switch settings Jumper switch Position Description JP1 Inserted on left side on R models Removed on others PCI to RACEway Bridge Reset Configuration JP2 Removed ECO SPROM Write...

Страница 28: ...switch is connected to the P_BOOT pin on the bridge Non Transparent Mode the primary secondary port has boot priority when the switch is ON OFF Transparent Mode Not Used 2 Serial EEPROM Access Enable...

Страница 29: ...abled when the switch is OFF TABLE 2 4 PCI to VME bridge SW5 settings Switch Function 1 8 VME CS CSR Base Address Switches 1 8 are connected to VME addresses A 28 21 Use 0x00 for AutoId TABLE 2 5 PCI...

Страница 30: ...ON enables the Serial EEPROM Autoload process TABLE 2 7 Processor Subsystem SW10 Switch Function 1 Processor MFS Serial EEPROM Write Enable ON to write enable the Processor MFS Serial EEPROM 2 Proces...

Страница 31: ...interface cause the board to reset Board reset does not generate a RACEway reset Jumper inserted on the right side Reset on RACEway interface cause the PXB to reset Board reset generates a RACEway re...

Страница 32: ...the System Controller Consequently system controller functions are also enabled Power Consumption Typical values for power consumption are shown in Table 2 10 In Idle Mode no processors are booting an...

Страница 33: ...d in the numbers below since the additional power is dissipated outside the board Furthermore the VME traffic pattern and the M5000 s share of the VME bus is highly application dependent TABLE 2 10 M5...

Страница 34: ...ed Air Cooleda Level 1 Level 2 Level 3 Part number extension A0 B1 C2H Temperat ure Operationalb at sea level 0 C to 50 C 300 lfm air lflow 0 C to 50 C 300 lfm air lflow Model Dependent 40 C to 75 C 6...

Страница 35: ...45 Figure 2 3 shows which spacer you need for the different configurations FIGURE 2 3 I O Configuration PMC 1 PMC 2 Power Fail Ethernet 1 2 1 2 Link 10 100 Serial Eth FC1 FC2 VM ETRO Duplex Fibre Chan...

Страница 36: ...nects to the 1 UART This cable is crossed and is the standard cable shipped with standard models 601 M5x10 2xRS232 split cable has two 9 pin D SUBs The D SUB on the short cable end connects to the fir...

Страница 37: ...Pin 5 RxD1 TxD1 GND RxD2 TxD2 LEMO Male DB9 Female To Board M5x10 2xRS232 Pin 2 Pin 3 Pin 5 RxD1 TxD1 GND DB9 Female Pin 2 Pin 3 Pin 5 RxD2 TxD2 GND Port 1 RS 232 Port 2 RS 232 Pin 2 Pin 1 Pin 7 Pin...

Страница 38: ...ription RJ45 Ethernet Connector The M5000 board has an RJ45 type connector for connecting to Ethernet FIGURE 2 5 Ethernet connector To connect to ethernet cables with RJ45 connectors must be used Cat...

Страница 39: ...25 M5000 Series User Guide Issued June 20 2007 3 Processor Subsystem...

Страница 40: ...Controller 3 PCI6540 PCIX to PCIX bridge via its primary side IDSEL Assignment AD 17 is used for the AMCC 440GX Processor IDSEL AD 18 is used for the PCI6540 PCIX to PCIX Bridge Primary Side IDSEL AD...

Страница 41: ...hips are used as the data memory banks One 2 byte wide memory chip is used as the parity bank only 8 data lines are used by the processor All the memory chips are 8 or 16MiB x 16 bits x 4 banks UART a...

Страница 42: ...are physically connected to LEDs The LEDs are labeled Duplex Link and 10 100 Table 3 1 shows their status values Status LEDs for EMAC1 EMAC2 and EMAC3 The LED signal lines for any second or third 10 1...

Страница 43: ...Green Yellow steady 100 Mbit s Link Green Yellow flashing 100 Mbit s Activity RX TX Green Green steady Duplex Link Green Green flashing Collision Not lit Yellow steady 10 Mbit s Link EMAC 2 and EMAC 3...

Страница 44: ...s used to store the MFS Midas File System Monitor and BSP boot behavior depending on parameter values held in the MFS Use of SPROM Devices should be under VMETRO guidance some functions are already av...

Страница 45: ...ted loop or point to point topologies The ISP2312 is a fully autonomous device capable of managing multiple I O operations and associated data transfers from start to finish without host intervention...

Страница 46: ...transparent modes are the only supported modes The transparent mode is the default mode A dip switch is used to select between transparent and non transparent mode In non transparent mode you can cho...

Страница 47: ...une 20 2007 M5000 Series User Guide PCI X to PCI X Bridges Secondary Interface The secondary interface of the PCI6540 is connected to the first PMC site PMC 1 and the primary interface of another PCI6...

Страница 48: ...34 M5000 Series User Guide Issued June 20 2007 Processor Subsystem...

Страница 49: ...35 M5000 Series User Guide Issued June 20 2007 4 PMC Subsystem...

Страница 50: ...The factory settings of the board switch configuration allows the bus frequency of the PCI X segments to be automatically configured to the frequency used by a PMC card insterted into it and by the l...

Страница 51: ...switch settings Arbitration Secondary and Tertiary PCI Segments The built in PCI X arbiter of the PCI6540 PCIX to PCIX Bridge is used The arbiter provides two REQ GNT pairs to the PMC to support a du...

Страница 52: ...signal to an unused AD line Support for System Processor in the PPMC site Monarch Support for having the system processor in the PPMC site is partially supported The MONARCH signal is controlled by a...

Страница 53: ...run in PCI or PCI X modes See PCI X Capability Selection for PMC Slots on page 11 Secondary Port Arbiter Setup As the only built in arbiter present on the secondary PCI bus the PCI6540 internal arbite...

Страница 54: ...nnector This connection follows the ANSI VITA 35 2000 standard PMC P4 pin out mapping to VME P0 and VME64x P2 As for the PMC 1 P4 to VME P2 connection signals are routed as differential pairs PMC 2 P4...

Страница 55: ...41 M5000 Series User Guide Issued June 20 2007 5 Extension Subsystem...

Страница 56: ...s are located on a private 64 bit 33MHz 5V signaling PCI only segment This PCI segment is called the Quaternary PCI Segment A PCI6540 universal PCI X to PCI X bridge connects the Quaternary PCI Segmen...

Страница 57: ...cated on the Quaternary PCI Segment Tundra Universe IID PCI to VME bridge Mercury PXB PCI to RACE bridge PCI6540 PCI X to PCI X bridge Arbitration The built in arbiter of the PCI6540 bridge is used to...

Страница 58: ...lementation multi beat transactions and support for bus parking Universe II provides high performance on the PCI bus Power up Reset Configuration The following options can be set at power up or reset...

Страница 59: ...or the PCI local bus In the second type of application the PXB is used to implement a transparent PCI to PCI bridge through the RACEway fabric In this application the PCI system designer uses the PXB...

Страница 60: ...5000 Series User Guide Issued June 20 2007 Extension Subsystem 5 5 Mezzanine Connector The mezzanine connector extends the Quaternary PCI Segment to a MEZZ x500F type mezzanine which contains 3 PMC sl...

Страница 61: ...ignals and configuration switches Secondary port this PCI segment is setup to run in the 64 bit 33MHz PCI mode Secondary Port Arbiter Setup The PCI6540 internal arbiter is used to arbitrate the PCI bu...

Страница 62: ...48 M5000 Series User Guide Issued June 20 2007 Extension Subsystem...

Страница 63: ...the M52xx and Mezzanine PMC Carrier board Only leave the board on surfaces with controlled static characteristics i e specially designed anti static table covers When handing the board to another per...

Страница 64: ...CI segment which is bridged to the Quarternary PCI bus via a transparent P2P bridge Note The Mezzanine PMC Carrier provides three 5v PMC sites The two PMC sites on the M52xx are 3 3v If 3 3v PMC sites...

Страница 65: ...51 Issued June 20 2007 M5000 Series User Guide Board Layout 6 2 Board Layout FIGURE 6 2 Board Layout Secondary MEZZ Bridge P2P PMC 5 PMC 4 PMC 3 PMC 5 connectors PMC 4 connectors PMC 3 connectors...

Страница 66: ...e by pushing them out from the backside of the front panel Step 1 Remove the Mezzanine PMC Carrier board from the M52xx 1 Remove the four screws that attach the PMC Carrier board to the M52xx board Th...

Страница 67: ...r on a smooth static protected work surface 2 Install the PMC modules in the PMC Carrier PMC position 3 is the upper position PMC position 4 is the middle position PMC position 5 is the lower position...

Страница 68: ...PMC Carrier board to the M52xx using screws as shown in Figure 6 3 PMC Carrier Daisy Chain The P1 connector of the PMC Carrier board provides a daisy chain bypass for the signals BG 3 0 and IACKIO Th...

Страница 69: ...PCI buses use a separate address space for initialization called the Configuration Space This address space uses the addressing signal IDSEL to select the target for all transactions The standard way...

Страница 70: ...will distribute these interrupts to the base board interrupt destinations according to the routing tables in Interrupt Routing on page 66 FIGURE 6 5 Carrier Board Interrupts TABLE 6 3 Interrupt routi...

Страница 71: ...rcuitry which is not normally used but can be used for very low level debugging This circuitry includes Two debug LEDs A status register where the value of the interrupt signals from the PMC slots are...

Страница 72: ...NC NC 6 GND NC BG1IN 1 NC NC 7 NC NC BG1OUT 1 NC NC 8 GND NC BG2IN 1 NC NC 9 NC NC BG2OUT 1 NC NC 10 GND NC BG3IN 1 NC NC 11 NC NC BG3OUT 1 NC NC 12 GND NC NC NC NC 13 NC NC NC NC NC 14 GND NC NC NC...

Страница 73: ...n4 5 23 Jn4 4 18 13 Jn4 4 20 Jn4 5 26 5V Jn4 5 25 Jn4 4 19 14 GND Jn4 5 28 NC Jn4 5 27 Jn4 4 21 15 Jn4 4 23 Jn4 5 30 NC Jn4 5 29 Jn4 4 22 16 GND Jn4 5 32 NC Jn4 5 31 Jn4 4 24 17 Jn4 4 26 Jn4 5 34 NC J...

Страница 74: ...rier MEZZ x500F PMC Connector Pinouts Jn1 Jn2 and Jn3 for all PMC slots on MEZZ x500F The pinouts for PMC connectors Jn1 Jn2 and Jn3 on the MEZZ x500F all three PMC slots are the same as for the PMC c...

Страница 75: ...10 11 P2 Z7 P2 D8 12 13 P2 D9 P2 Z9 14 15 P2 D10 P2 D11 16 17 P2 Z11 P2 D12 18 19 P2 D13 P2 Z13 20 21 P2 D14 P2 D15 22 23 P2 Z15 P2 D16 24 25 P2 D17 P2 Z17 26 27 P2 D18 P2 D19 28 29 P2 Z19 P2 D20 30...

Страница 76: ...6 P2 A6 12 13 P2 C7 P2 A7 14 15 P2 C8 P2 A8 16 17 P2 C9 P2 A9 18 19 P2 C10 P2 A10 20 21 P2 C11 P2 A11 22 23 P2 C12 P2 A12 24 25 P2 C13 P2 A13 26 27 P2 C14 P2 A14 28 29 P2 C15 P2 A15 30 31 P2 C16 P2 A1...

Страница 77: ...63 M5000 Series User Guide Issued June 20 2007 7 Miscellaneous Functions...

Страница 78: ...segments Processor CPLDs Other JTAG devices Each segment is used for a specific set of similar devices and can be accessed separately from the remaining parts of the JTAG chain This allows tools that...

Страница 79: ...VME reset RACEway reset and PMC modules etc The following devices are considered as possible reset sources 2 PPMC sites TUNDRA Universe II VME to PCI bridge MERCURY PXB Race to PCI Bridge 3 PCI6540 PC...

Страница 80: ...line X 3 PCI6540 PCIX to PCIX bridges 2 interrupt lines P and S ISP2312 PCIX to Dual FC Host Adapter 2 interrupt lines A and B MERCURY PXB PCI to Race Bridge 4 interrupt lines A B C and D The followi...

Страница 81: ...PPC P2P Bridge 1 P2P Bridge 2 P2P Bridge 3 A B C D A B C D A B C D I0 I1 X P S P S P S A A C B B D A C C B D A C X S P D B D I0 I1 P S P S Destination Source PPMC1 PPMC2 MEZZ PXB PPC P2P Bridge 1 P2P...

Страница 82: ...ed in the middle of the board The PowerPC processor communicates with the sensors via its second I2C bus The type of component used is Maxim MAX1731 Contact VMETRO for more information Interrupt routi...

Страница 83: ...ies User Guide Power Supplies 7 4 Power Supplies The main sources of power are 5V and 12V supplied by the VME backplane The 5V power source is used to generate the required component voltages 12V is r...

Страница 84: ...70 M5000 Series User Guide Issued June 20 2007 Miscellaneous Functions...

Страница 85: ...71 Issued June 20 2007 M5000 Series User Guide APPENDIXES...

Страница 86: ...72 M5000 Series User Guide Issued June 20 2007...

Страница 87: ...73 M5000 Series User Guide Issued June 20 2007 A PLD Registers...

Страница 88: ...T_A Interrupt Register 0x04 R 8 bits INTERRUPT_B Interrupt Register 0x05 R 8 bits INTERRUPT_C Interrupt Register 0x06 R 8 bits INTERRUPT_D Interrupt Register 0x07 R 8 bits INTERRUPT_E Interrupt Regist...

Страница 89: ...mory bank 0 or not 1 Read Only 7 ECO_SPROM_WE ECO SPROM device is write protected 1 or enabled 0 Read Only Note Only present from ECO C1 2 SYS_RST System Reset Set this bit to 1 to reset the entire bo...

Страница 90: ...herwise 33MHz or 100MHz 3 PMC1_CLK1 PMC 1 PCI X Bus Clock Speed Bit 1 Read Only set to 1 if clock speed detected on PCI X bus where PMC site 1 is located is over 66MHz 0 otherwise 2 PMC1_CLK0 PMC 1 PC...

Страница 91: ...ddress TABLE A 3 Interrupt Registers Address Register 7 4 Register 3 0 0x04 PPC Ethernet 0x05 P2P1_P P2P2_P 0x06 P2P3_P P2P1_S 0x07 P2P2_S P2P3_S 0x08 FC_A FC_B 0x09 PMC1_A PMC1_B 0x0A PMC1_C PMC1_D 0...

Страница 92: ...78 M5000 Series User Guide Issued June 20 2007 PLD Registers...

Страница 93: ...79 M5000 Series User Guide Issued June 20 2007 B Universe IID Configuration Examples...

Страница 94: ...ping of the data lanes on all transactions between VMEbus and PCI bus This is also the case for accesses to the internal registers The internal register bank is located on the PCI side of the byte swa...

Страница 95: ...e Image examples are shown in Figure B 1 FIGUREB 1 Configuration example for VMEbus slave images PCI bus VMEbus VME Slave Image 0 VMEbus A16 supervisor AM codes 0x4FFF 0x0000 UNIVERSE IID PCI bus Conf...

Страница 96: ...supervisory accesses in the address range 0x0 0x4FFF from VMEbus to Configuration Cycles on the PCI bus 1 This column shows write data for configuration from PCI TABLE B 1 VME_RAI Setup Action Result...

Страница 97: ...BLE B 3 VME Slave image 1 setup Write from VME PCI Data 1 Result D 0x0000 1000 to A 0x000F18 0x0010 0000 Base Address set to 0x100000 D 0x0000 4000 to A 0x000F1C 0x0040 0000 Bound Address set to 0x400...

Страница 98: ...002 VSI_0 Enable Image VAS A16 LAS Config Space PGM both SUPER Supervisor other options disabled D 0x0000 1000 to A 0x000F18 0x0010 0000 VSI_1 Base Address set to 0x100000 D 0x0000 4000 to A 0x000F1C...

Страница 99: ...OS bits located in the PCI_CSR register offset 0x004 must be set to allow the Universe II to respond to PCI memory and I O commands FIGUREB 2 Configuration example for PCI slave images PCI bus VMEbus...

Страница 100: ...6 PCI slave image 0 setup Write from VME PCI Data 1 Result D 0x0000 0000 to A 0x000104 0x0000 0000 Base Address set to 0x0000 0000 D 0x0010 0000 to A 0x000108 0x0000 1000 Bound Address set to 0x0000 1...

Страница 101: ...07 PCI Target Enable bits set this write cycle also sets the PCI master enable bit if it is disabled ref VMEbus Slave Image section D 0x0000 0000 to A 0x000104 0x0000 0000 LSI_0 Base Address set to 0x...

Страница 102: ...88 M5000 Series User Guide Issued June 20 2007 Universe IID Configuration Examples...

Страница 103: ...guration ROM A VME64 Configuration SPROM is included in the board design This SPROM is accessible from the processor via a set of I O pins on the third PCIX to PCIX bridge The general content layout i...

Страница 104: ...byte Use D16 or D08 EO every byte used Use D32 D16 or D08 EO every byte used Reserved for future use Not to be used 17 0x00 0x01 0x80 0x81 0x82 0x83 0x84 0x85 0xFE 0xFF Not to be used Reserved for fu...

Страница 105: ...ion ID VMETRO Assigned 57 00 0x000000 No string 5B 00 5F 7B 00 Reserved for future use 7F 0x00 0x01 0x02 0x4F 0x50 7F 0x80 EF 0xF0 FE 0xFF Not used No program ID ROM only Manufacturer defined User def...

Страница 106: ...e Channel 3 RS 232 Ethernet 2x Fibre Channel 4 RS 232 2x Fibre Channel 5 RS 232 1x Fibre Channel 8 RS 422 9 RS 422 Ethernet 10 RS 422 Ethernet 1x Fibre Channel 11 RS 422 Ethernet 2x Fibre Channel 12 R...

Страница 107: ...5 Revision ID Description Field Bits Description Family Specific Number 31 16 Reserved PCB Revision 15 12 PCB Revision number Start at 0xA and wrap from 0xF to 0x0 Reserved 11 8 0000 ECO Level 7 0 ECO...

Страница 108: ...94 M5000 Series User Guide Issued June 20 2007 VME64 Configuration ROM...

Страница 109: ...95 M5000 Series User Guide Issued June 20 2007 D VME Connector Pinout...

Страница 110: ...ued June 20 2007 VME Connector Pinout D 1 General Description The abbreviation NC means Not Connected The description Jn4 1 Jn4 2 etc used in the pinout table for P2 connector means the pins 1 2 etc o...

Страница 111: ...ink A Pair 2 Rx 8 C5 Link A Pair 2 Tx 9 B5 Link A Pair 1 Rx 10 A5 Link A Pair 1 Tx 11 E6 Link A Pair 1 Rx 12 D6 Link A Pair 1 Tx 13 C6 Link A Pair 0 Rx 14 B6 Link A Pair 0 Tx 15 A6 Link A Pair 0 Rx 16...

Страница 112: ...A15 Link C Pair 0 Rx 46 E16 Link C Pair 0 Tx 47 D16 Link C Pair 0 Rx 48 C16 Link C Pair 0 Tx 49 B16 Link D Pair 3 Rx 50 A16 Link D Pair 3 Tx 51 E17 Link D Pair 3 Rx 52 D17 Link D Pair 3 Tx 53 C17 Link...

Страница 113: ...9 NC GND BG2OUT GND NC 10 GND SYSCLK BG3IN SYSFAIL NC 11 NC GND BG3OUT BERR NC 12 GND DS1 BR0 SYSRESET NC 13 NC DS0 BR1 LWORD NC 14 GND WRITE BR2 AM5 NC 15 NC GND BR3 A 23 NC 16 GND DTACK AM0 A 22 NC...

Страница 114: ...10 GND NC A 30 NC Jn4 15 11 Jn4 17 NC A 31 NC Jn4 16 12 GND NC GND NC Jn4 18 13 Jn4 20 NC 5V NC Jn4 19 14 GND NC D 16 NC Jn4 21 15 Jn4 23 NC D 17 NC Jn4 22 16 GND NC D 18 NC Jn4 24 17 Jn4 26 NC D 19 N...

Страница 115: ...O NC 11 NC pIO05 A 31 GND NC 12 GND pIO03 GND pREQI NC 13 NC GND 5V pREQO NC 14 GND pRDCON D 16 GND NC 15 NC pPAR D 17 pIO02 NC 16 GND GND D 18 pIO01 NC 17 NC pIO00 D 19 GND NC 18 GND pIO15 D 20 pIO12...

Страница 116: ...102 M5000 Series User Guide Issued June 20 2007 VME Connector Pinout...

Страница 117: ...103 M5000 Series User Guide Issued June 20 2007 E PMC Connector Pinout...

Страница 118: ...connected to 5V via a pull up resistor or to ground GND via a pull down resistor respectively Connections to the VME P2 connector are denoted as P2 row pin Example P2 D1 means connection to pin 1 in r...

Страница 119: ...5 INTB 6 INTC 7 BUSMODE1 8 5V 9 INTD 10 NC PCI RSVD 11 GND 12 NC PCI RSVD 13 CLK 14 GND 15 GND 16 GNT 17 REQ 18 5V 19 V I O 20 AD 31 21 AD 28 22 AD 27 23 AD 25 24 GND 25 GND 26 C BE 3 27 AD 22 28 AD...

Страница 120: ...7 GND 8 NC PCI RSVD 9 NC PCI RSVD 10 NC PCI RSVD 11 PU BUSMODE2 12 3 3V 13 RST 14 PD BUSMODE3 15 3 3V 16 PD BUSMODE4 17 NC PCI RSVD 18 GND 19 AD 30 20 AD 29 21 GND 22 AD 26 23 AD 24 24 3 3V 25 IDSEL...

Страница 121: ...6 C BE 5 7 C BE 4 8 GND 9 V I O 10 PAR64 11 AD 63 12 AD 62 13 AD 61 14 GND 15 GND 16 AD 60 17 AD 59 18 AD 58 19 AD 57 20 GND 21 V I O 22 AD 56 23 AD 55 24 AD 54 25 AD 53 26 GND 27 GND 28 AD 52 29 AD 5...

Страница 122: ...10 A5 A3 ATX1 Link A Pair 1 Transmit data 11 C6 E3 ARX1 Link A Pair 1 Receive data 12 A6 B3 ATX1 Link A Pair 1 Transmit data 13 C7 D4 ARX0 Link A Pair 0 Receive data 14 A7 A4 ATX0 Link A Pair 0 Trans...

Страница 123: ...ata 46 A23 A15 CTX0 Link C Pair 0 Transmit data 47 C24 E15 CRX0 Link C Pair 0 Receive data 48 A24 B15 CTX0 Link C Pair 0 Transmit data 49 C25 D16 DRX3 Link D Pair 3 Receive data 50 A25 A16 DTX3 Link D...

Страница 124: ...110 M5000 Series User Guide Issued June 20 2007 PMC Connector Pinout...

Страница 125: ...ent reliability Values are calculated for different environments but this does not mean that operation in this environment is supported These environments are GB Ground Benign Locations with controlle...

Страница 126: ...BLE F 1 MTBF Values Hours Model GB 25 C GF 35 C NS 40 C AIC 50 C ARW 50 C ARW 75 C M5210RP EFF 1 259 400 635 280 399 230 195 230 116 280 48 307 M5210 JEJ 1 021 000 551 000 361 000 173 000 112 000 46 0...

Страница 127: ...C 440GX PowerPC Processor 133 MHz PCI X PMC Positions High Speed Streaming Memory RJ45 10 100 Ethernet Optical 2Gb s Fibre Channel RJ45 Gigabit Ethernet Optical Gigabit Ethernet M5210 EF0 1 2 256MiB 1...

Страница 128: ...flash files such as mmon ini and vxbsp ini Detailed description of all symptoms observed including serial port output and analyzer trace files if applicable Information about 3rd party drivers and HW...

Страница 129: ...www ansi org Component Manufacturers Vendor Component Available documentation Tundra http www tundra com Universe II VME PCI Bridge User Manual Manual Addendum Device Errata Application Notes AMCC htt...

Страница 130: ...116 M5000 Series User Guide Issued June 20 2007...

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