
Manual VIPA System 300S SPEED7
Chapter 5 Deployment I/O periphery
HB140E - CPU SC - RE_313-6CF03 - Rev. 07/45
5-27
In the CPU a comparison value may be stored that is assigned to the digital
output, to the status bit "Status Comparator" STS_CMP and to the
hardware interrupt. The digital output may be activated depending on the
count value and comparison value. A comparison value may be entered by
the parameter assignment screen form respectively by the request
interface of the SFB 47.
You pre-define the behavior of the counter output via the parameterization:
•
output never switches
•
output switch when counter value
≥
comparison value
•
output switch when counter value
≤
comparison value
•
output switch at comparison value
No comparison
The output is set as normal output. The SFB input parameter CTRL_DO is
effect less. The status bits STS_DO and STS_CMP (Status comparator in
the instance DB) remain reset.
Count
≥
comparison value
respectively
Count
≤
comparison value
The output remains set as long as the counter value is higher or equal
comparison value respectively lower or equal comparison value. For this
the control bit must be set.
The comparison result is shown by the status bit STS_CMP.
This status bit may only be reset if the comparison condition is no longer
fulfilled.
Pulse at comparison value
When the counter reaches the comparison value the output is set for the
parameterized pulse duration. If you have configured a main count
direction the output is only activated when the comparison value is reached
with the specified main count direction. For this the control bit CTRL_DO
should be set first.
The status of the digital output may be shown by the status bit ST_DO.
The comparison result is shown by the status bit STS_CMP. This status bit
may only be reset if the pulse duration has run off. comparison condition is
no longer fulfilled.
With pulse time = 0 the output is as set as the comparison condition is
fulfilled.
Pulse duration
For adaptation to the used actors a pulse duration may be specified. The
pulse duration defines how long the output should be set. It may be preset
in steps of 2ms between 0 and 510ms. The pulse duration starts with the
setting of the according digital output. The inaccuracy of the pulse duration
is less than 1ms.
There is no past triggering of the pulse duration when the comparison
value has been left and reached again during pulse output. A change of the
pulse period during runtime is not applied until the next pulse.
Comparator
Characteristics of
the output
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Страница 40: ...Chapter 3 Hardware description Manual VIPA System 300S SPEED7 3 14 HB140E CPU SC RE_313 6CF03 Rev 07 45 ...
Страница 122: ...Chapter 5 Deployment I O periphery Manual VIPA System 300S SPEED7 5 36 HB140E CPU SC RE_313 6CF03 Rev 07 45 ...
Страница 140: ...Chapter 6 Deployment PtP communication Manual VIPA System 300S SPEED7 6 18 HB140E CPU SC RE_313 6CF03 Rev 07 45 ...