VeEX VePal TX130M+, Руководство пользователя

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Master and Slave Clock ID:
This field is not configurable; it will be populated with the clock ID of the 1588 Master and
Slave once the 1588 protocol exchange is established. This will be indicated by the 1588 top icon becoming green.
The Clock ID is formatted as the MAC address of the device first 3 byte -- FF -- FE -- last 3 byte of MAC address.
The MAC address of the device can be manually changed in Tool > IP menu.
Note: The in master clock mode supports only ONE slave clock.
Sync Rate
(Master and unicast slave only)
:
Defines the sync packet sending rate, values from 0.625 packets per second
to 64.
Sync rate (Master):
Sets the rate of the multicast Sync messages sent by the master, values from 0.625
packets/second to 64.
Sync rate (unicast slave):
Sets the Sync messages rate requested by the slave to the master, values from 0.625
packets/second to 64.
Announce Int:
Interval of the announcement message to be sent by the master clock. Options are 1, 2, 4, 8, and
16seconds.
DelayReq Rate:
Defines the DelayReq/DelayResp messages rate, values from 0.625 packets per second to 64.
Domain Number:
Enable/Disable. Enabling this feature allows the user to assign a domain number to a slave-master
network. The domain number limit is 255.
Transfer Mode:
Select between Unicast or Multicast mode.
In multicast mode, the Master Clock will send multicast PTP messages.
In unicast mode, the Master and Slave clocks will exchange unicast PTP messages. If Unicast is selected, Master Clock's
IP address needs to be entered.
Slave-emulation and Slave-sync only options
Master Address
(unicast only)
:
Tap on the field and use the soft-keyboard to enter the master IP address.
MIN Filter:
Select between Disabled or enter the length of the filter (2,4,6,8,12).
The filter is designed to compensate for network jitter by averaging the PTP messages timing values before updating the
slave recovered clock. The length of the filter determines the number of samples averaged. Larger filter size will slow
down the convergence speed of the slave. In condition of no or low network jitter it is recommended to disable the Filter.
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Reference Clock
Master Emulation and Master Sync Modes:
The 1588v2 PTP Master can be clocked with an internal or external clock
source.
Clock Input Port (1588 Master Mode Only):
If a non-internal clock source is chosen, the external reference clock is
connected through the AuxRx port.
Clock Source:
Select between an internal or external clock source. Possible external clock sources can be: 2 MHz,
2Mbps (E1 signal), 10MHz, 25MHz, 125MHz or GPS (1 pps).
The external clock source is connected to the RX2-Unbal port, this port is marked Aux Rx on the connector panel.
Reference Clock Output:
The reference clock used by the 1588v2 Master or the recovered clock from the 1588v2 Slave
can be regenerated out of the PDH TX port (marked Tx on the connector panel) with a different clock format in order to
synchronize other network elements.
The clock can be formatted to: 2Mbps (E1 signal), 2.048MHz, 1.544Mbps (T1 signal), 1.544MHz,10MHz, 25MHz, and
125MHz.
Port:
Tx1 - Unbalanced or Tx1 - Balanced
Line Code:
HDB3 or AMI
E1 Framing:
Unframed, PCM31, PCM31C, PCM30, or PCM30C
PRBS Pattern
Invert
Press Start to Start the test.
Indicator Symbols
An M or S indicates that the test set is in Master or Slave Mode. A green 1588 icon indicates that the 1588 test is running. If the
icon is flashing or solid red, there may be an issue with setup and the test will not work.
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