TOSHIBA
TMPR3904F Rev. 2.0
118
26
bus ownership requests, the SREQ has a higher priority than the GREQ. Therefore, the priority
between the two DMAC modules depends on the daisy-chain connection when the bus
ownership request mode is the same, and it depends on the bus ownership request mode when
the kinds of the bus ownership differ.
10.2.2 DMAC internal blocks
The following Figure 10-2 shows the internal blocks of DMAC0.
Fig. 10-2 DMAC Internal Blocks
10.2.3 Priority between modules
In the priority between the modules, there are the priority by the daisy-chain and the priority by
the difference in the kinds of bus ownership.
(1) Priority by daisy-chain
Channel 1
Source Address Register
Destination Address Register
Byte Count Register
31
0
Channel 0
DMA Control Register
Data Holding Register
Channel Status Register
Next Byte Count Register
Channel Control Register
Содержание TMPR3904F
Страница 1: ...Users Manual 32bit RISC Microprocessor TX39 family TMPR3904F Rev 2 0 Jan 12 1998 ...
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Страница 9: ...Users Manual 01 1 INTRODUCTION 1 1 Overview ...
Страница 10: ...Users Manual 02 1 2 Notation used in this manual Mathematical notation Data notation Signal notation ...
Страница 11: ...Users Manual 03 1 3 Kind of accessing by the TX3904 ...
Страница 12: ...Users Manual 04 1 4 Precautions in the TMPR3904F specification Don t set Don t use ...
Страница 13: ...Users Manual 05 Do not use ...
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Страница 15: ...Users Manual 7 2 FEATURES n n n n n n n n n n n n n ...
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Страница 19: ...Users Manual 11 4 PINS 4 1 Positions of Pins ...
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Страница 21: ...Users Manual 13 4 2 Functions of Pins ...
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