TMP91C824
91C824-131
(12) Timing generation
#
In UART Mode
Receiving
Mode
9-Bit
(Note)
8-Bit
+
Parity (Note)
8-Bit, 7-Bit + Parity, 7-Bit
Interrupt timing
Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Framing error timing
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
―
Center of last bit
(parity bit)
Center of last bit
(parity bit)
Overrun error timing
Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Transmitting
Mode
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Interrupt timing
Just before stop bit is
transmitted
Just before stop bit is
transmitted
Just before stop bit is transmitted
"
I/O interface
SCLK Output Mode
Immediately after rise of last SCLK signal.
(See figure 3.9 19.)
Transmission
Interrupt
timing
SCLK Input Mode
Immediately after rise of last SCLK signal Rising Mode, or immediately
after fall in Falling Mode. (See figure 3.9 20.)
SCLK Output Mode
Timing used to transfer received to data Receive Buffer 2 (SC0BUF) (i.e.
immediately after last SCLK). (See figure 3.9 21.)
Receiving
Interrupt
timing
SCLK Input Mode
Timing used to transfer received data to Receive Buffer 2 (SC0BUF) (i.e.
immediately after last SCLK). (See figure 3.9 22.)