6-5
Themis Computer
6—Resets
Reset Sources
An incoming VMEbus reset may be enabled or disabled through the setting of
jumper
JP1601
. If JP1601 is ON, the USPII
e
-USB can see the reset from the VME-
bus. If JP1601 is OFF or left open, resets from the VMEbus will be ignored. The
incoming
VMESYS
reset is controlled further by the
vme_reset_mode
control
register in the PLD.
Outgoing VMEbus resets may also be enabled and disabled by setting jumper
JP1501
. If JP1501 is ON, a reset of the USPII
e
-USB will be propagated from the
Universe II distributed to the VMEbus. If JP1501 is OFF or left open, a reset of the
USPII
e
-USB will not be propagated to the VMEbus.
Software may initiate a VMEbus Reset by writing to the
VME_Software_Reset
address located at 0x1FF.F110.0001. A software VMEbus reset will reset only the
VMEbus. No components on the USPII
e
-USB are effected by a software VMEbus
reset.
6.3.4
2-Level Watchdog Resets
A 2-Level Watchdog reset, as explained in Section 5.4 on page 5-3, is implemented
in the PLD. When the second watchdog in the PLD expires, the PLD asserts a POR
to the UltraSPARC-II
e
. This signal initiates a POR in the processor, which propa-
gates throughout the system.
6.3.5
Software POR
Software may initiate a reset equivalent to a Power-On-Reset (POR) by setting the
SOFT_POR bit in the UltraSPARC-II
e
Reset_Control Register (see
Table 6-1
on
page 6-6). This bit will remain set until the software clears it, to allow software to
detect the source of the reset.
Note:
This 2-Level Watchdog is different from a Watchdog implemented inter-
nally on the UltraSPARC-II
e
. Refer to “Watchdog Reset (WDR)”, page 6-3, for
more information concerning the Watchdog Reset implemented internally on the
UltraSPARC-II
e
.
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