USPIIe-USB Hardware Manual
3-6
Themis Computer
3.1.7
PLD
The PLD (Programmable Logic Device) on the USPII
e
-USB resides on the Ebus of
the Sun Rio I/O Controller. There are two main functions of this PLD: one is to
implement miscellaneous registers and manipulate the address map of the Flash
devices; the other is to implement the reset logic.
3.1.8
Acer Super I/O Controller
The Acer (M1535D) Super-I/O controller chip controls AC97 (Audio Codec 97)
audio, the IEEE 1284 parallel port, the PS/2 keyboard/mouse, and both TTYA and
TTYB serial ports. Each component is individually configured to maximize the per-
formance of the USPII
e
-USB.
3.1.9
Seimens SAB 82532 Controller
The Seimens SAB 82532 Enhanced Serial Communication Controller provides sup-
port for Serial Ports C and D. A maximum external data transfer rate of 10
Mbits/second and a maximum internal data transfer rate of 2 Mbits/second is attain-
able on each port.
3.1.10
Flash Memory
The USPII
e
-USB includes three (3) Flash EPROM devices (4-MB). They are
located on the Baseboard bottom side (solder side) and are accessible through the
Baseboard Ebus2. Any Flash can be jumper configurable as the boot device. The
boot Flash normally contains Sun's OBP or Wind River's VxWorks boot ROM. The
mapping of each Flash is largely configurable by the PLD. It is also possible to
divide each flash into two (2) sections, permitting a total of eight (8) boot devices.
3.1.11
TOD and NVRAM
The Non-Volatile RAM and a Time of Day (TOD) clock are both contained in the
timekeeper chip (SGS-Thomson, M48T59Y-70MH1). The NVRAM has its own
lithium battery to operate the clock and maintain the contents of the NVRAM during
power-off situations. The battery device is an SGS Thomson M4T28-BR12SH1.
This single lithium battery provides backup for approximately 10 years, and the real-
time clock circuitry provides accuracy of +/- one (1) second per day.
NVRAM and TOD are programmed using the FORTH toolkit in the OpenBoot
PROM (OBP). To learn how to replace the battery, consult Section 1.6,
“TOD/NVRAM Battery Replacement,” on page 1-14.
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