DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
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SLAU580B – June 2014 – Revised September 2016
Copyright © 2014–2016, Texas Instruments Incorporated
TSW14J10 FMC-USB Interposer Card
6.3
ADC12J4000EVM With Xilinx VC707 Development Board Setup Example
The following is an example of the TSW14J10EVM being used to test the ADC12J4000EVM with a Xilinx
Virtex VC707 development platform as shown in
.
Figure 18. ADC12J4000EVM, TSW14J10EVM and VC707 Board
The following example shows the required modifications in the ADC12J4000 GUI for a setup using the
JESD204B mode setting of LMFS = 8885 (8 lanes, 8 converters, 8 octets/frame, 5 samples/frame) with
the ADC in bypass mode, and a sample rate of 4G.
Setup the hardware per
but using the ADC12J4000EVM. Setup the hardware per the
ADC12J4000EVM User’s Guide
), internal clock mode, but use a 600-MHz IF connected to V
IN
.
Use the ADC12J4000EVM GUI A, shown in
, and follow steps 3.4–3.9 and 3.11 in the
ADC12J4000EVM User’s Guide
to configure the ADC EVM.
