DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
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SLAU580B – June 2014 – Revised September 2016
Copyright © 2014–2016, Texas Instruments Incorporated
TSW14J10 FMC-USB Interposer Card
6
DAC and ADC GUI Configuration File Changes When Using a Xilinx Development
Platform
The configuration files that come with the TI ADC and DAC EVM GUIs are setup to operate with the
Altera-based TI TSW14J56EVM. These files will work with the TSW14J10EVM when using a Xilinx
platform but need a couple of changes to the settings of the LMK04828 registers. The firmware for the
Xilinx Development Platforms use a separate clock input for REFCLK and Core clock to give maximum
flexibility and support all line rates and subclasses with a single programmable design. The Xilinx IP used
in the firmware can be driven by a single clock in many circumstances (see the clocking section of the
Xilinx IP product guide for more details).
The REFCLK and Core clock are determined by the following lane rate conditions:
REFCLK = Lane rate / 10, and Core clock = Lane rate / 10 when lane rate is between 1 G and 3.2 G
REFCLK = Lane rate / 20 and Core clock = Lane rate / 40 when lane rate is between 3.2 G and
10.3125 G*
Note: The GTEX2 transceivers with speed grade -2 devices used on the Xilinx development platforms
have a maximum rate of 10.3125 Gbps. In addition, the KC705 transceivers have a frequency band gap
from 8 Gbps to 9.8 Gbps.
The ADC and DAC GUIs do not always use the same LMK04828 outputs for these two clocks. The output
from the LMK04828 connected to FMC connector pins D4 and D5 will be the REFCLK. The output from
the LMK04828 connected to FMC connector pins G6 and G7 will be the Core clock. Consult the EVM
schematic to verify the outputs.
On the KC705 platform, only 4 TX and 4 RX JESD204B lanes were routed to the HPC FMC connector.
On the VC707 and ZC706, there are at least 8 RX and TX lanes routed. The Xilinx firmware designed to
be used with the TSW14J10EVM running HSDC Pro GUI uses internal FPGA memory only. Due to both
of these constraints, the user must be careful when selecting the number of samples and number of lanes
to be used in both ADC and DAC testing. The total memory and JESD204B lanes that are available are as
follows:
KC705 4 lanes RX and TX 128K total samples
VC707 8 lanes RX and TX 256K total samples
ZC706 8 lanes RX and TX 128K total samples
For example when using the KC705, if the user is capturing data from a dual ADC, the most lanes that
can be used is 4 and the highest value that can be entered for number of samples in HSDC Pro GUI will
be 64K.
