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8-24.
PSC1 Module Control n Register (MDCTLn) Field Descriptions
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9-1.
Power Management Features
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10-1.
Master IDs
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10-2.
Default Master Priority
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10-3.
System Configuration Module 0 (SYSCFG0) Registers
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10-4.
System Configuration Module 1 (SYSCFG1) Registers
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10-5.
Revision Identification Register (REVID) Field Descriptions
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10-6.
Device Identification Register 0 (DEVIDR0) Field Descriptions
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10-7.
Boot Configuration Register (BOOTCFG) Field Descriptions
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10-8.
Kick 0 Register (KICK0R) Field Descriptions
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10-9.
Kick 1 Register (KICK1R) Field Descriptions
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10-10. Host 0 Configuration Register (HOST0CFG) Field Descriptions
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10-11. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
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10-12. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
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10-13. Interrupt Enable Register (IENSET) Field Descriptions
.............................................................
10-14. Interrupt Enable Clear Register (IENCLR) Field Descriptions
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10-15. End of Interrupt Register (EOI) Field Descriptions
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10-16. Fault Address Register (FLTADDRR) Field Descriptions
...........................................................
10-17. Fault Status Register (FLTSTAT) Field Descriptions
................................................................
10-18. Master Priority 0 Register (MSTPRI0) Field Descriptions
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10-19. Master Priority 1 Register (MSTPRI1) Field Descriptions
..........................................................
10-20. Master Priority 2 Register (MSTPRI2) Field Descriptions
..........................................................
10-21. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
...............................................
10-22. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
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10-23. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
...............................................
10-24. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
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10-25. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
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10-26. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
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10-27. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
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10-28. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
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10-29. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
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10-30. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
...............................................
10-31. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
............................................
10-32. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
............................................
10-33. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
............................................
10-34. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
............................................
10-35. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
............................................
10-36. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
............................................
10-37. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
............................................
10-38. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
............................................
10-39. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
............................................
10-40. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
............................................
10-41. Suspend Source Register (SUSPSRC) Field Descriptions
.........................................................
10-42. Chip Signal Register (CHIPSIG) Field Descriptions
.................................................................
10-43. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
...................................................
10-44. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
...................................................
10-45. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
...................................................
10-46. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
...................................................
10-47. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
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15
SPRUGX5A
–
May 2011
List of Tables
Copyright
©
2011, Texas Instruments Incorporated
Содержание AM1802
Страница 1: ...AM1802 ARM Microprocessor System Reference Guide Literature Number SPRUGX5A May 2011 ...
Страница 2: ...2 SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...
Страница 30: ...30 ARM Subsystem SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...
Страница 144: ...144 Power Management SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...