SE867-AGPS User Guide
1VV0300860 Rev. 3 - 2010-05-10
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved
page 16 of 69
5.1.2.
hat the V_IO is now
change in the V_IO
supply control the
t the same logic is
s respecting the
condition of IOVDD_AIN being the higher voltage in the system. In this configuration,
the internal regulator with input VDD_REG_IN is not exploited in order to have
IOVDD_AIN connected to the 1V8_DIG voltage and 1.8V logic levels on the WAKE1 pin.
The diagram below indicates the connections required for this configuration.
Configuration 2
This configuration is similar to the previous one with the difference t
set to 1.8V and the I/O logic levels have changed consequently. This
levels requires also a change in the IOVDD_AIN supply. Indeed this
logic level of the WAKE1 pin and so, in order to have all the I/O pin a
necessary to change also the IOVDD_AIN configuration, although alway
Figure 2 Power supply connections for configuration 2
The VIN voltage range is the same reported for the previous configuration. Please
consider that in place of exploiting the internally generated 1V8_DIG an external 1.8V
supply is allowed to be used as well (in this case please verify to have a not noisy and
clear 1.8V supply). The voltage range for this external 1.8V supply is 1.62V ÷ 1.98V.
Note: Please note that the diagram above reports only the required connections.
For detailed circuit with all the required components (including bypass and
decoupling capacitors) please refer to the suggested designs.
