SE867-AGPS User Guide
1VV0300860 Rev. 3 - 2010-05-10
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved
page 19 of 69
5.2.
ule. When using a
be paid in order to
deed applying 3V
GPS chipset with a
er to allow correct
ommendations an
ntion must be paid
ervals.
tion. At the power
t signal must be asserted, after the reset signal is received the
module is forced in a power-on state and boots up at the negation of the reset signal.
ignal must be asserted also when a power fault is detected in the 1V8_DIG
der to avoid conditions which can cause corruption of the internal flash
memory. The reset signal can be asserted by either an external power-on-reset
supervisor or a host proce
5.3.
Logic levels
Power-On Sequence
A few rules must be respected when powering the SE867-AGPS mod
configuration with a 3V power supply on the V_IO pin attention must
avoid asserting V_IO when the 1V8_DIG is not asserted as well. In
without the core voltage will cause improper internal biasing of the
subsequent large current flow and potential device damage. In ord
power-on of the module and according to the chipset vendor rec
internal network on the V_IO power has been inserted. However atte
in order to avoid asserting V_IO without 1V8_DIG asserted for long int
Furthermore, the module requires a power-on reset and fault detec
up the active low rese
The reset s
signal in or
ssor.
Digital Signals
Item
Condition
Min
Max
Unit
VIH
VDDIO
10%
0.7 x
VDDIO
V
VIL
VDDIO
10%
0.3 x
VDDIO
V
VOH
IOH = -3.5mA @3V
10% VDDIO
IOH = -2.25mA @1.8V
10% VDDIO
0.8 x
VDDIO
VDDIO
V
VOL
IOL = 3.5mA @3V
10% VDDIO
IOL = 2.25mA @1.8V
10% VDDIO
GND
0.2 x
VDDIO
V
RESET: Schmitt trigger low to
high threshold VT+
VDDIO = 1.8V
10%
0.85
1.4
V
RESET: Schmitt trigger high to
low threshold VT-
VDDIO = 1.8V
10%
0.53
1.05
V
RESET: Schmitt trigger
hysteresis window
VDDIO = 1.8V
10%
0.12
0.64
V
1V8_RF_EN High
1.2
V
1V8_RF_EN Low
0.3
V
1V8_DIG_EN High
1.2
V
1V8_DIG_EN Low
0.3
V
