SE867-AGPS User Guide
1VV0300860 Rev. 3 - 2010-05-10
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved
page 14 of 69
5.
Electrical description
Having power supply circuitry, RF path and board layout properly designed is key to get
a successfully application design. So, the below requirements and guidelines have to be
carefully read and taken into account for correct device operations.
5.1.
Available power supply configurations
In order to give a higher flexibility to the required power configuration, different
powering options have been devised:
1)
Wide range voltage input from 2.5V up to 4.2V plus an additional 3V
10%
reference voltage for I/O peripherals (for 3V logic level interfaces)
2)
Wide range voltage input from 2.5V up to 4.2V plus an additional 1.8V
10%
reference voltage (internally or externally generated) for I/O peripherals (for 1.8V
logic level interfaces)
3)
Externally generated 1.8V
5% supply plus 3V
10% or 1.8V
10% for I/O
peripherals (bypassing the internal regulator). This solution allows for a lower
flexibility but assures lower power consumptions (no dissipation in the internal
linear regulator).
5.1.1.
Configuration 1
The first available power supply configuration exploits the internal voltage regulators to
generate the required 1V8_DIG and 1V8_RF supplies. In order to do so, the internal
regulators must be enabled via the 1V8_DIG_EN and 1V8_RF_EN signals (active low).
Additional 3V voltage must be supplied on the V_IO pin (this voltage regulate the I/O
voltage levels for the UART signals). VDD_REG_IN pin and IOVDD_AIN must be tied
together and must be equal to or greater than every other voltage supplied to the
internal GPS chipset (they must be compared with V_IO and VDD_CTRL but not with VIN
because VIN is internally regulated). VDD_CTRL is responsible of powering the
SYSCTRL island and must be connected with the output of the internal regulator
(VREG_OUT). SYSCTRL island includes the RFEN, RFXEN and RESET signals, plus the
RTC circuitry (so it’s responsible of the system powering during power save modes
involving the RTC). The diagram reported in the figure below shows the power
connections for this configuration.
