Tektronix TMSST1, Инструкция по эксплуатации

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Specifications
2--2
TMSST1 775-Pin Socket Hardware Support
The TMSST1 probe adapter hardware derives several custom signals from the
front-side bus signals captured by the ASIC. These signals are used by the logic
analyzer support software to provide clocking, transaction phase linking, and
disassembly. Following is a description of these custom signals:
PHASE_D. This signal can be used by the logic analyzer to store only bus cycles
that contain active information. The PHASE_D signal is asserted when any of the
following signals are asserted: ADS#, DRDY#, INIT#, RESET#, RS[2:0]#, and
SNOOP_D.
TRACK_ERR_D.
This signal is asserted whenever the request or snoop counters
exceed their maximum or a minimum value. This signal is also asserted when
ADS# has been observed active for two clock cycles in a row.
The probe adapter uses passive series isolation to acquire data.
The probe adapter uses a bus tracking PAL to aid the disassembly software in
linking various bus phases.
The IA32G9 software allows disassembly from a data bus operating at the
common clock rate specified in Table 2--1 on page 2--4. The setup and hold
sample points are set to default timing numbers based on FSB specifications.
Derived Signals
Signal Probing
Bus Tracking Logic
Common Clock