Tektronix TLA715 Series, Руководство по обслуживанию

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Specifications
TLA715 Dual Monitor Portable Mainframe Service Manual
1- 9
Table 1- 4: Latencies (Cont.)
Characteristic Description
Intermodule latencies for DSO source (typical)
DSO source characteristics
DSO to LA intermodule System
Trigger (TTLTRG7)
1
DSO: Trigger All Modules
LA: If anything, Do nothing
--240 ns
DSO to DSO intermodule System
Trigger (TTLTRG7)
1
DSO1: Trigger All Modules
DSO: Wait for System Trigger
50 ns
DSO to LA intermodule ARM
(TTLTRG2 ,4, 5, 6)
2
--192 ns + Clk
DSO to DSO intermodule ARM
(TTLTRG2 ,4, 5, 6) 59 ns
DSO to LA intermodule Signal 1, 2
(ECLTRG0, 1)
2, 3
DSO: Trigger and set Sig1
LA: Wait for Sig1, then trigger
--179 ns + Clk
DSO to LA intermodule Signal 3, 4
(TTLTRG0, 1)
2
DSO: Trigger and set Sig3
LA: Wait for Sig3, then trigger
--184 ns + Clk
1
In the Waveform window, triggers are always marked immediately except when delayed to the first sample. In the Listing
window, triggers are always marked on the next sample period following their occurrence.
2
Clk represents the time to the next master clock at the destination logic analyzer module. In the normal internal clock
mode, this represents the delta time to the next sample clock. In the external clock mode, this represents the time to the
next master clock generated by the setup of the clocking state machine and the supplied target system clocks and
qualification data.
3
Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode of operation where only one source is allowed to drive the
signal node at any one time. The signal source can be used to drive any combination of destinations.
4
All system trigger and signal input latencies are measured from the falling edge transition (active/true low) with signals in
the wired-OR configuration.
5
Smpl represents the time from the event to the next valid data sample at the LA probe tip. In the normal internal clock
mode, this represents the delta time to the next sample clock. In the MagniVu internal clock mode, this represents 500 ps
or less. In the external clock mode, this represents the time to the next master clock generated by the setup of the
clocking state machine and the supplied target system clocks and qualification data.
6
All Signal output latencies are validated to the rising edge of an active (true) high output.