Tektronix TLA715 Series, Руководство по обслуживанию

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Specifications
TLA715 Dual Monitor Portable Mainframe Service Manual
1- 5
Table 1- 3: Backplane interface
Characteristic Description
Slots 4 C-size, compliant with VXIBus System Spec Rev. 1.4, except as follows:
MODID driver not capable of sinking 48 mA as required for 3-state lines (meets standard
design practices for VXI); and
TTLTRG~ may not be unasserted after SYSRESET~, as ADG332 does not use
SYSRESET~ (accommodated by local controller reset)
n
CLK10 Frequency 10 MHz
±
100 PPM
Relative time correlation error
(typical) Typical measured relative time correlation error between modules in the same instrument
Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a simple,
overall, typical value. Assumes standard accessory probes are used.
For long-term (> 1 s) time interval measurements between modules add 0.01% of the delta
time between the absolute time measurements to the relative time correlation error to account
for the inaccuracy of the CLK10 source.
LA to LA MagniVu data 2 ns
LA to LA normal data using an
internal clock
1
1 LA Smpl -- 0.5 ns
LA to LA normal data using an
external clock 2 ns
LA to LA MagniVu to DSO data
2
3 ns
LA normal data using an internal
clock to DSO
1, 2
1 LA Smpl
±
2 ns
LA normal data using an external
clock to DSO
2, 3
3 ns
DSO to DSO
2
3 ns
Intermodule signal line bandwidth Minimum bandwidth up to which the intermodule signals operate correctly
Signal 1, 2 (ECLTRG0, 1) 50 MHz squarewave
Signal 3, 4 (TTLTRG0, 1) 10 MHz squarewave
System trigger input TTL-compatible via rear panel BNC connector
Input destination System Trigger (TTLTRG7)
Input levels V
IH
≥
2.0 V
V
IL
≤
0.8 V
Input mode Falling edge sensitive, latched (active low)
Minimum pulse width 12 ns
Active period Accepts system triggers during valid acquisition periods via real-time gating; resets system
trigger input latch between valid acquisition periods
Maximum input voltage 0 to 5 V peak