Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 37 / 145

37
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
Feature ARC HS36 ARC HS38x2
Maximum
CPU frequency 100 MHz 100 MHz
PAE
The ARC HS38x2 core supports Physical Address Extension (PAE). PAE extends the
phys
ical address range beyond the core’s native 32-bit, 4GByte address range. In the
AXC003, the PAE functionality is used to extend the physical address range from 4 to 8 GByte.
A high- level overview of the memory map is shown in Figure 23. The memory map for the
lower 4GByte of the physical address range is fully programmable via control registers. The
sections “
Controlling the Memory Map
” and “
Software Interfaces
” provide additional
information.
The memory map for the extended part of the physical address range is fixed, and used for
DDR only. The AXC003 supports 2 GByte of DDR.
AXC003 Memory Map