Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 120 / 145

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DesignWare ARC AXC003 CPU Card User Guide ARC RTT Address Decoder Registers
Synopsys, Inc. Version 6323-018
May 2017
9.4 ARC RTT Address Decoder Registers
RTT_A_SLV0: ARC RTT Slave Select Register 0
Address offset:
0x1040
Reset value:
0x1111_1111
Table 11 RTT_A_SLV0 Register
Legend: * reset value
Bit Name Access Value Description
3:0
SLV_SEL0
RW Slave select for address aperture[0]
0
no slave selected
1*
slave 1 selected (=> DDR controller)
2
slave 2 selected (=> SRAM controller)
3
slave 3 selected (=> AXI tunnel)
4
slave 4 selected (=> AXI2APB bridge)
5
slave 5 selected (=> ROM Controller)
6
slave 6 selected (=> IOC port)
7
Reserved
7:4
SLV_SEL1
RW
1*
Slave select for address aperture[1]
1)
11:8
SLV_SEL2
RW
1*
Slave select for address aperture[2]
1)
15:12
SLV_SEL3
RW
1*
Slave select for address aperture[3]
1)
19:16
SLV_SEL4
RW
1*
Slave select for address aperture[4]
1)
23:20
SLV_SEL5
RW
1*
Slave select for address aperture[5]
1)
27:24
SLV_SEL6
RW
1*
Slave select for address aperture[6]
1)
31:28
SLV_SEL7
RW
1*
Slave select for address aperture[7]
1)
1) Same encoding as SLV_SEL0
RTT_A_SLV1: ARC RTT Slave Select Register 1
Address offset:
0x1044
Reset value:
0x1111_1111
Table 12 RTT_A_SLV1 Register
Legend: * reset value
Bit Name Access Value Description
3:0 RW Slave select for address aperture[8]