Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 109 / 145

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Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
BYPASS bypass the input divider
NOUPDATE prevent update of the PLL with new settings. Debug only; can be used for
register RW test
To obtain a 50% duty-cycle the divider shall be programmed as follows:
- even divider ratio => LOWTIME = HIGHTIME
EDGE =
0
- odd divider ratio => LOWTIME = HI 1
EDGE =
1
9.1.1.2 TUN_PLL_FBDIV Register
31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIME
Address offset: 0x0044
Reset Value: 0x0000_03CF (0x0000_03CF after pre-boot)
Access: RW
Register to control setting of the Tunnel PLL feedback divider
LOWTIME[5:0] sets the amount of time in VCO cycles that the feedback clock remains low
HIGHTIME[5:0] sets the amount of time in VCO cycles that the feedback clock remains high
FBDIV = L HIGHTIME
VCOFREQ = (33MHz / IDIV) * FBDIV
EDGE chooses the edge that the High Time counter transitions on (0=rising,
1=falling)
BYPASS bypass the feedback divider
NOUPDATE prevent update of the PLL with new settings. Debug only; can be used for
register RW test
To obtain a 50% duty-cycle the divider shall be programmed as follows:
- even divider ratio => LOWTIME = HIGHTIME
EDGE =
0
- odd divider ratio => LOWTIME = HI 1
EDGE =
1