Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 46 / 145

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DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview
Synopsys, Inc. Version 6323-018
May 2017
ICTL_MB
INT_STATUS Register Bit
Interrupt Source
25
HAPS Extension 1 interrupt
(signal
HE_intr[1]
at connector)
Clock
The AXC003 CPU Card has two clock inputs from which all other clocks are derived internally:
33 MHz reference clock
AXI tunnel clock
These clocks are provided at the HapsTrak II connectors on the bottom side of the AXC003
CPU Card.
Figure 28 on page 47 shows the top-level clock architecture. The 33-MHz input
clock is supplied to the CGU. The CGU generates all the internal clocks using the internal
PLLs and clock dividers of the FPGA. The main clock domains are highlighted by the different
colors in Figure 28. The AXC003 Processor FPGA has the following main clock domains:
33 MHz clock
This is the input clock of the AXC003 Processor FPGA. All other clocks are derived
from this clock. The only exception is the source-synchronous input clock for the
AXI tunnel.
DDR reference clock
This is the reference clock for the DDR3 controller and PHY. This clock is used to
generate the 400 MHz DDR memory clock and the different internal clock phases (0°,
90°, 180°, 270°). The AXI bus runs at a quarter of the DDR memory clock frequency,
that is, at 100 MHz.
ARC HS core clock
APB clock
AXI Tunnel clock