108
Synopsys, Inc.
Version 6323-018
May 2017
9
Software Interfaces
This section describes the control registers inside the AXC003 Processor FPGA. Add the
address offset listed for each register to the base address of the AXI2APB bridge (default
address: 0xF000_0000) to obtain the register address.
9.1 Clock-Generation Registers
This section describes the registers used for clock generation.
TUNNEL PLL
Reference input clock for Tunnel PLL is 33Mhz
Minimum input clock frequency is 10MHz
VCO range for Tunnel PLL is 600 - 1440MHz
9.1.1.1 TUN_PLL_IDIV Register
31
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
NOUPDATE
BYPASS
EDGE
HIGHTIME
LOWTIME
Address offset: 0x0040
Reset Value:
0x0000_2041
(0x0000_3001 after pre-boot)
Access:
RW
Register to control setting of the Tunnel PLL input divider
LOWTIME[5:0] sets the amount of time in input cycles that the divided input clock remains
low
HIGHTIME[5:0] sets the amount of time in input cycles that the divided input clock remains
high
IDIV = L HIGHTIME
EDGE
chooses the edge that the High Time counter transitions on (
0
=rising,
1
=falling)