Sun Microsystems SunSwift SPARCserver 1000, Руководство по обслуживанию

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B-4 SPARCserver 1000 System Service Manual—June 1996
B
Because the system boards are identical, an external arbitrator must determine
which board can access the system bus at any instant. The external arbitrator is
called the central arbiter (CARB), which is located on the control board.
B.4 SuperSPARC Module
Figure B-4 is a block diagram of the SuperSPARC module. Each board supports
up to two SuperSPARC modules. Each module contains one processor
integrated circuit (SMXX), cache memory, an MX cache memory controller
(MXCC) and a (BW) interface. Main memory banks are on the system board.
Figure B-4 Processor Module Block Diagram
B.5 I/O Unit
Figure B-5 shows the I/O section of the system board, which is called the I/O
unit. The I/O unit includes an SBus Interface (SBI) chip, an IOCache (IOC), and
an I/O memory management unit, known as the External Page Table (XPT).
SBus addresses are translated into memory and I/O addresses by the I/O
memory management unit, which is controlled by the SBus interface chip.
External cache memory
Processor
XDBus (on system board)
S
R
A
M
CC
BW
SMXX
Cache memory controller
Processor module connector
XBus
BootBus