Sun Microsystems SunSwift SPARCserver 1000, Руководство по обслуживанию

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Functional Description B-5
B
Figure B-5 I/O Unit Block Diagram
B.6 Main Memory Unit
Figure B-6 shows the system board main memory section (the main memory unit).
Each system board contains one memory queue handler (MQH). Each MQH
controls up to 16 SIMMs using four programmable decode registers located in the
MQH. These registers can be programmed to handle DRAMs with densities from
1 Mbit to 256 Mbit. The memory described by one decode register is known as a
group and the memory controlled by one MQH is called a bank. Because each
decode register describes the memory in a group, it is possible for the decode
registers for a single MQH to handle SIMMs of different densities if their timing
characteristics are the same. See Appendix A for a more detailed description of
SIMMs and SIMM groups.
Figure B-6 Main Memory Unit Block Diagram
B.7 Control Board
Figure B-7 is a detailed control board block diagram. One control board serves
the entire system regardless of the number of system boards. The control board
generates all system-wide clocks. The central arbiters (CARBS) arbitrate
disputes between the BARBS on the system boards that compete for use of the
system bus. LEDs on the board edge display the power and signal status.
SBus
XBus
XDBus (on
system board)
I/O cache
External page table
SBI
SBus Slot 1 SBus Slot 2 SBus Slot 3
ESC, logical SBus Slot 0
XDBus (on system board)
Memory queue handler (MQH)
SIMMs
Group 0 Group 1 Group 2 Group 3