Sun Microsystems SunSwift SPARCserver 1000, Руководство по обслуживанию

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B-2 SPARCserver 1000 System Service Manual—June 1996
B
for the XDbus and four bus interface chips (BICs). Also included are two bus
watchers (BW), a memory queue handler (MQH), I/O cache (IOC), and an
SBus interface (SBI) component.
Figure B-2 System Board Components
B.2 System Architecture
Figure B-3 is a detailed block diagram of SPARCserver 1000 architecture. Each
SPARCserver 1000 supports 1 to 8 SuperSPARC modules, 1 to 4 SBusses and 0
to 12 SBus cards, 0 to 3 on each system board. Memory capacity is 32 Mbytes to
2 Gbytes.
Functionally, the SPARCserver 1000 consists of six main sections: processor,
memory, I/O, bus interface, bootbus interface, and clock generation. The main
sections of the system are interconnected by the system bus (called the XDBus).
The XDBus is the main system bus located on the backplane and system board.
BICs interconnect the backplane XDBus with the XDBus on the system board.
XDBus is supported by four BICs, which are 18-bit, bit-sliced pipeline registers.
SuperSPARC module
connectors
SIMMs
BARB
BIC BIC BIC BIC
XDBus connector
BW
BW
IOC
MQH
SBI
SBus connectors